erc32/start/boardinit.S

0001 /**
0002  * @file
0003  *
0004  * @ingroup sparc_erc32
0005  *
0006  * @brief Initialise various ERC32 registers
0007  */
0008
0009 /*
0010  *  COPYRIGHT (c) 2000.
0011  *  European Space Agency.
0012  *
0013  *  The license and distribution terms for this file may be
0014  *  found in the file LICENSE in this distribution or at
0015  *  http://www.rtems.org/license/LICENSE.
0016  */
0017
0018 #include <rtems/asm.h>
0019 #include <erc32.h>
0020
0021         .global __bsp_board_init
0022 __bsp_board_init:
0023
0024 /* Check if MEC is initialised. If not, this means that we are
0025    running on the simulator. Initiate some of the parameters
0026    that are done by the boot-prom otherwise.
0027 */
0028
0029         set     SYM(ERC32_MEC), %g3  ! g3 = base address of peripherals
0030     ld  [%g3], %g2
0031     set 0xfe080000, %g1
0032     andcc   %g1, %g2, %g0
0033     bne 2f
0034
0035  /* Stop the watchdog */
0036
0037     st  %g0, [%g3 + SYM(ERC32_MEC_WATCHDOG_TRAP_DOOR_SET_OFFSET)]
0038
0039  /* Set zero waitstates */
0040
0041     st  %g0, [%g3 + SYM(ERC32_MEC_WAIT_STATE_CONFIGURATION_OFFSET)]
0042
0043  /* Set the correct memory size in MEC memory config register */
0044
0045     set SYM(PROM_SIZE), %l0
0046     set 0, %l1
0047     srl %l0, 18, %l0
0048 1:
0049     tst %l0
0050     srl %l0, 1, %l0
0051     bne,a   1b
0052     inc %l1
0053     sll %l1, 8, %l1
0054
0055     set SYM(RAM_SIZE), %l0
0056     srl %l0, 19, %l0
0057 1:
0058     tst %l0
0059     srl %l0, 1, %l0
0060     bne,a   1b
0061     inc %l1
0062     sll %l1, 10, %l1
0063
0064                                            ! set the Memory Configuration
0065         st     %l1, [ %g3 + ERC32_MEC_MEMORY_CONFIGURATION_OFFSET ]
0066
0067     set SYM(RAM_START), %l1  ! Cannot use RAM_END due to bug in linker
0068     set SYM(RAM_SIZE), %l2
0069     add %l1, %l2, %sp
0070
0071     set SYM(CLOCK_SPEED), %g6   ! Use 14 MHz in simulator
0072     set 14, %g1
0073     st  %g1, [%g6]
0074
0075 2:
0076
0077  /* Initialise timer */
0078
0079     set SYM(_ERC32_MEC_Timer_Control_Mirror), %l2
0080     st  %g0, [%l2]
0081     st  %g0, [%g3 + SYM(ERC32_MEC_TIMER_CONTROL_OFFSET)]
0082
0083  /* Enable power-down */
0084
0085     ld  [%g3 + SYM(ERC32_MEC_CONTROL_OFFSET)], %l2
0086     or  %l2, ERC32_CONFIGURATION_POWER_DOWN_ALLOWED, %l2
0087     st  %l2, [%g3 + SYM(ERC32_MEC_CONTROL_OFFSET)]
0088
0089     retl
0090     nop
0091
0092 /* end of file */