erc32/include/tm27.h

0001 /* SPDX-License-Identifier: BSD-2-Clause */
0002
0003 /**
0004  * @file
0005  * @ingroup sparc_erc32
0006  * @brief Implementations for interrupt mechanisms for Time Test 27
0007  */
0008
0009 /*
0010  *  COPYRIGHT (c) 2006.
0011  *  Aeroflex Gaisler AB.
0012  *
0013  * Redistribution and use in source and binary forms, with or without
0014  * modification, are permitted provided that the following conditions
0015  * are met:
0016  * 1. Redistributions of source code must retain the above copyright
0017  *    notice, this list of conditions and the following disclaimer.
0018  * 2. Redistributions in binary form must reproduce the above copyright
0019  *    notice, this list of conditions and the following disclaimer in the
0020  *    documentation and/or other materials provided with the distribution.
0021  *
0022  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
0023  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
0024  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
0025  * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
0026  * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
0027  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
0028  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
0029  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
0030  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
0031  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
0032  * POSSIBILITY OF SUCH DAMAGE.
0033  */
0034
0035 #ifndef _RTEMS_TMTEST27
0036 #error "This is an RTEMS internal file you must not include directly."
0037 #endif
0038
0039 #ifndef __tm27_h
0040 #define __tm27_h
0041
0042 /*
0043  *  Define the interrupt mechanism for Time Test 27
0044  *
0045  *  NOTE: Since the interrupt code for the SPARC supports both synchronous
0046  *        and asynchronous trap handlers, support for testing with both
0047  *        is included.
0048  */
0049
0050 #define ERC32_BSP_USE_SYNCHRONOUS_TRAP  0
0051
0052 /*
0053  *  The synchronous trap is an arbitrarily chosen software trap.
0054  */
0055
0056 #if (ERC32_BSP_USE_SYNCHRONOUS_TRAP == 1)
0057
0058 #define TEST_VECTOR SPARC_SYNCHRONOUS_TRAP( 0x90 )
0059
0060 #define MUST_WAIT_FOR_INTERRUPT 1
0061
0062 #define TM27_USE_VECTOR_HANDLER
0063
0064 #define Install_tm27_vector( handler ) \
0065   set_vector( (handler), TEST_VECTOR, 1 );
0066
0067 #define Cause_tm27_intr() \
0068   __asm__ volatile( "ta 0x10; nop " );
0069
0070 #define Clear_tm27_intr() /* empty */
0071
0072 #define Lower_tm27_intr() /* empty */
0073
0074 /*
0075  *  The asynchronous trap is an arbitrarily chosen ERC32 interrupt source.
0076  */
0077
0078 #else   /* use a regular asynchronous trap */
0079
0080 #define TEST_INTERRUPT_SOURCE ERC32_INTERRUPT_EXTERNAL_1
0081 #define TEST_INTERRUPT_SOURCE2 (ERC32_INTERRUPT_EXTERNAL_1+1)
0082
0083 #define MUST_WAIT_FOR_INTERRUPT 1
0084
0085 static inline void Install_tm27_vector( rtems_interrupt_handler handler )
0086 {
0087   (void) rtems_interrupt_handler_install(
0088     TEST_INTERRUPT_SOURCE,
0089     "tm27 low",
0090     RTEMS_INTERRUPT_SHARED,
0091     handler,
0092     NULL
0093   );
0094   (void) rtems_interrupt_handler_install(
0095     TEST_INTERRUPT_SOURCE2,
0096     "tm27 high",
0097     RTEMS_INTERRUPT_SHARED,
0098     handler,
0099     NULL
0100   );
0101 }
0102
0103 #define Cause_tm27_intr() \
0104   do { \
0105     ERC32_Force_interrupt( TEST_INTERRUPT_SOURCE+(Interrupt_nest>>1) ); \
0106     nop(); \
0107     nop(); \
0108     nop(); \
0109   } while (0)
0110
0111 #define Clear_tm27_intr() \
0112   ERC32_Clear_interrupt( TEST_INTERRUPT_SOURCE )
0113
0114 #define Lower_tm27_intr() /* empty */
0115
0116 #endif
0117
0118 #endif