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Warning, /bsps/sparc/erc32/README.md is written in an unsupported language. File is not indexed.

0001 erc32
0002 =====
0003 Description of SIS as related to this BSP
0004 
0005 
0006 ```
0007 BSP NAME:           sis
0008 BOARD:              any based on the European Space Agency's ERC32
0009 BUS:                N/A
0010 CPU FAMILY:         sparc
0011 CPU:                ERC32 (SPARC V7 + on-CPU peripherals)
0012                     based on Cypress 601/602
0013 COPROCESSORS:       on-chip 602 compatible FPU
0014 MODE:               32 bit mode
0015 
0016 DEBUG MONITOR:      none
0017 ```
0018 
0019 PERIPHERALS
0020 -----------
0021 ```
0022 TIMERS:
0023   NAME:             General Purpose Timer  
0024   RESOLUTION:         50 nanoseconds - 12.8 microseconds
0025   NAME:             Real Time Clock Timer  
0026   RESOLUTION:         50 nanoseconds - 3.2768 milliseconds
0027   NAME:             Watchdog Timer  
0028   RESOLUTION:         XXX
0029 SERIAL PORTS:       2 using on-chip UART
0030 REAL-TIME CLOCK:    none
0031 DMA:                on-chip
0032 VIDEO:              none
0033 SCSI:               none
0034 NETWORKING:         none
0035 ```
0036 
0037 DRIVER INFORMATION
0038 ------------------
0039 ```
0040 CLOCK DRIVER:       ERC32 internal Real Time Clock Timer
0041 IOSUPP DRIVER:      N/A
0042 SHMSUPP:            N/A
0043 TIMER DRIVER:       ERC32 internal General Purpose Timer
0044 CONSOLE DRIVER:     ERC32 internal UART 
0045 ```
0046 
0047 STDIO
0048 -----
0049 ```
0050 PORT:               Channel A
0051 ELECTRICAL:         na since using simulator
0052 BAUD:               na
0053 BITS PER CHARACTER: na
0054 PARITY:             na
0055 STOP BITS:          na
0056 ```
0057 
0058 Notes
0059 -----
0060 ERC32 BSP only supports single processor operations.
0061 
0062 A nice feature of this BSP is that the RAM and PROM size are set in the 
0063 linkcmds file and the startup code programs the Memory Configuration
0064 Register based on those sizes.
0065 
0066 The Watchdog Timer is disabled.
0067 
0068 This code was developed and tested entirely using the SPARC Instruction 
0069 Simulator (SIS) for the ERC32.  All tests were known to run correctly
0070 against sis v1.7.
0071 
0072 
0073 Memory Map
0074 ----------
0075 ```
0076 0x00000000 - 0x00000000 + _PROM_SIZE      code and initialized data
0077 0x01f80000                                on chip peripherals
0078 0x00000000 - 0x02000000 + _RAM_SIZE       destination for initialized data
0079                                           BSS (i.e. unitialized data)
0080                                           C Heap (i.e. malloc area)
0081                                           RTEMS Workspace
0082 
0083 The C heap is assigned all memory between the end of the BSS and the 
0084 RTEMS Workspace.  The size of the RTEMS Workspace is based on that 
0085 specified in the application's configuration table.
0086 ```
0087