shared/start/bspsmp-arm-psci.c

0001 /* SPDX-License-Identifier: BSD-2-Clause */
0002
0003 /**
0004  * @file
0005  *
0006  * @ingroup RTEMSBSPsShared
0007  *
0008  * @brief PSCI-based BSP CPU start.
0009  */
0010
0011 /*
0012  * Copyright (C) 2021 On-Line Applications Research Corporation (OAR)
0013  * Written by Kinsey Moore <kinsey.moore@oarcorp.com>
0014  *
0015  * Redistribution and use in source and binary forms, with or without
0016  * modification, are permitted provided that the following conditions
0017  * are met:
0018  * 1. Redistributions of source code must retain the above copyright
0019  *    notice, this list of conditions and the following disclaimer.
0020  * 2. Redistributions in binary form must reproduce the above copyright
0021  *    notice, this list of conditions and the following disclaimer in the
0022  *    documentation and/or other materials provided with the distribution.
0023  *
0024  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
0025  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
0026  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
0027  * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
0028  * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
0029  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
0030  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
0031  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
0032  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
0033  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
0034  * POSSIBILITY OF SUCH DAMAGE.
0035  */
0036
0037 #include <bsp/start.h>
0038 #include <bsp.h>
0039 #if defined( AARCH64_MULTILIB_ARCH_V8 ) || \
0040   defined( AARCH64_MULTILIB_ARCH_V8_ILP32 )
0041 #include <rtems/score/aarch64-system-registers.h>
0042 #else
0043 #include <rtems/score/aarch32-system-registers.h>
0044 #endif
0045
0046 #if defined( AARCH64_MULTILIB_ARCH_V8 ) || \
0047   defined( AARCH64_MULTILIB_ARCH_V8_ILP32 )
0048 #define REGISTER_PREFIX "x"
0049 #else
0050 #define REGISTER_PREFIX "r"
0051 #endif
0052
0053 bool _CPU_SMP_Start_processor( uint32_t cpu_index )
0054 {
0055 #if defined( AARCH64_MULTILIB_ARCH_V8 ) || \
0056   defined( AARCH64_MULTILIB_ARCH_V8_ILP32 )
0057   uint32_t PSCI_FN_SYSTEM_CPU_ON = 0xC4000003;
0058   uint64_t target_cpu = _AArch64_Read_mpidr_el1();
0059   uint64_t ret;
0060 #else
0061   uint32_t PSCI_FN_SYSTEM_CPU_ON = 0x84000003;
0062   uint32_t target_cpu = _AArch32_Read_mpidr();
0063   uint32_t ret;
0064 #endif
0065   target_cpu &= ~( 0xff0000ffUL );
0066   target_cpu |= cpu_index;
0067
0068   __asm__ volatile (
0069     "mov " REGISTER_PREFIX "0, %1\n"
0070     "mov " REGISTER_PREFIX "1, %2\n"
0071     "mov " REGISTER_PREFIX "2, %3\n"
0072     "mov " REGISTER_PREFIX "3, #0\n"
0073 #ifdef BSP_CPU_ON_USES_SMC
0074     "smc #0\n"
0075 #else
0076     "hvc #0\n"
0077 #endif
0078     "mov %0, " REGISTER_PREFIX "0\n"
0079     : "=r" ( ret ) : "r" ( PSCI_FN_SYSTEM_CPU_ON ), "r" ( target_cpu ),
0080     "r" ( _start )
0081     : REGISTER_PREFIX "0", REGISTER_PREFIX "1", REGISTER_PREFIX "2",
0082     REGISTER_PREFIX "3"
0083   );
0084
0085   return ret == 0;
0086 }