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File indexing completed on 2025-05-11 08:24:07 

0001 /* SPDX-License-Identifier: BSD-2-Clause */
0002 
0003 /* GRSPW ROUTER APB-Register Driver.
0004  *
0005  * COPYRIGHT (c) 2010-2017.
0006  * Cobham Gaisler AB.
0007  *
0008  * Redistribution and use in source and binary forms, with or without
0009  * modification, are permitted provided that the following conditions
0010  * are met:
0011  * 1. Redistributions of source code must retain the above copyright
0012  *    notice, this list of conditions and the following disclaimer.
0013  * 2. Redistributions in binary form must reproduce the above copyright
0014  *    notice, this list of conditions and the following disclaimer in the
0015  *    documentation and/or other materials provided with the distribution.
0016  *
0017  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
0018  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
0019  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
0020  * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
0021  * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
0022  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
0023  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
0024  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
0025  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
0026  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
0027  * POSSIBILITY OF SUCH DAMAGE.
0028  */
0029 
0030 #include <rtems.h>
0031 #include <rtems/libio.h>
0032 #include <rtems/bspIo.h>
0033 #include <stdio.h>
0034 #include <bsp.h>
0035 
0036 #include <drvmgr/drvmgr.h>
0037 #include <grlib/ambapp_bus.h>
0038 #include <grlib/grspw_router.h>
0039 
0040 #include <grlib/grlib_impl.h>
0041 
0042 //#define STATIC
0043 #define STATIC static
0044 
0045 #define UNUSED __attribute__((unused))
0046 
0047 //#define DEBUG 1
0048 
0049 #ifdef DEBUG
0050 #define DBG(x...) printf(x)
0051 #else
0052 #define DBG(x...) 
0053 #endif
0054 
0055 #define THREAD_SAFE 1
0056 
0057 #define REG_WRITE(addr, val) (*(volatile unsigned int *)(addr) = (unsigned int)(val))
0058 #define REG_READ(addr) (*(volatile unsigned int *)(addr))
0059 
0060 
0061 /*
0062  * ROUTER RTPMAP register fields
0063  */
0064 #define RTPMAP_PE (0x7fffffff << RTPMAP_PE_BIT)
0065 #define RTPMAP_PD (0x1 << RTPMAP_PD_BIT)
0066 
0067 #define RTPMAP_PE_BIT 1
0068 #define RTPMAP_PD_BIT 0
0069 
0070 /*
0071  * ROUTER RTACTRL register fields
0072  * DEFINED IN HEADER
0073  */
0074 
0075 /*
0076  * ROUTER PCTRL register fields
0077  * DEFINED IN HEADER
0078  */
0079 
0080 /*
0081  * ROUTER PSTSCFG register fields
0082  * DEFINED IN HEADER
0083  */
0084 
0085 /*
0086  * ROUTER PSTS register fields
0087  * DEFINED IN HEADER
0088  */
0089 
0090 /*
0091  * ROUTER PTIMER register fields
0092  */
0093 #define PTIMER_RL (0xffff << PTIMER_RL_BIT)
0094 
0095 #define PTIMER_RL_BIT 0
0096 
0097 /*
0098  * ROUTER PCTRL2 register fields
0099  * DEFINED IN HEADER
0100  */
0101 
0102 /*
0103  * ROUTER RTRCFG register fields
0104  */
0105 #define RTRCFG_SP (0x1f << RTRCFG_SP_BIT)
0106 #define RTRCFG_AP (0x1f << RTRCFG_AP_BIT)
0107 #define RTRCFG_FP (0x1f << RTRCFG_FP_BIT)
0108 #define RTRCFG_SR (0x1 << RTRCFG_SR_BIT)
0109 #define RTRCFG_PE (0x1 << RTRCFG_PE_BIT)
0110 #define RTRCFG_IC (0x1 << RTRCFG_IC_BIT)
0111 #define RTRCFG_IS (0x1 << RTRCFG_IS_BIT)
0112 #define RTRCFG_IP (0x1 << RTRCFG_IP_BIT)
0113 #define RTRCFG_AI (0x1 << RTRCFG_AI_BIT)
0114 #define RTRCFG_AT (0x1 << RTRCFG_AT_BIT)
0115 #define RTRCFG_IE (0x1 << RTRCFG_IE_BIT)
0116 #define RTRCFG_RE (0x1 << RTRCFG_RE_BIT)
0117 #define RTRCFG_EE (0x1 << RTRCFG_EE_BIT)
0118 #define RTRCFG_LS (0x1 << RTRCFG_LS_BIT)
0119 #define RTRCFG_SA (0x1 << RTRCFG_SA_BIT)
0120 #define RTRCFG_TF (0x1 << RTRCFG_TF_BIT)
0121 #define RTRCFG_ME (0x1 << RTRCFG_ME_BIT)
0122 #define RTRCFG_TA (0x1 << RTRCFG_TA_BIT)
0123 #define RTRCFG_PP (0x1 << RTRCFG_PP_BIT)
0124 #define RTRCFG_WCLEAR (RTRCFG_ME)
0125 
0126 #define RTRCFG_SP_BIT 27
0127 #define RTRCFG_AP_BIT 22
0128 #define RTRCFG_FP_BIT 17
0129 #define RTRCFG_SR_BIT 15
0130 #define RTRCFG_PE_BIT 14
0131 #define RTRCFG_IC_BIT 13
0132 #define RTRCFG_IS_BIT 12
0133 #define RTRCFG_IP_BIT 11
0134 #define RTRCFG_AI_BIT 10
0135 #define RTRCFG_AT_BIT 9
0136 #define RTRCFG_IE_BIT 8
0137 #define RTRCFG_RE_BIT 7
0138 #define RTRCFG_EE_BIT 6
0139 #define RTRCFG_LS_BIT 5
0140 #define RTRCFG_SA_BIT 4
0141 #define RTRCFG_TF_BIT 3
0142 #define RTRCFG_ME_BIT 2
0143 #define RTRCFG_TA_BIT 1
0144 #define RTRCFG_PP_BIT 0
0145 
0146 /*
0147  * ROUTER TC register fields
0148  */
0149 #define TC_RE (0x3f << TC_RE_BIT)
0150 #define TC_EN (0x3f << TC_EN_BIT)
0151 #define TC_CF (0x3f << TC_CF_BIT)
0152 #define TC_TC (0x3f << TC_TC_BIT)
0153 
0154 #define TC_RE_BIT 9
0155 #define TC_EN_BIT 8
0156 #define TC_CF_BIT 6
0157 #define TC_TC_BIT 0
0158 
0159 /*
0160  * ROUTER VER register fields
0161  */
0162 #define VER_MA (0xff << VER_MA_BIT)
0163 #define VER_MI (0xff << VER_MI_BIT)
0164 #define VER_PA (0xff << VER_PA_BIT)
0165 #define VER_ID (0xff << VER_ID_BIT)
0166 
0167 #define VER_MA_BIT 24
0168 #define VER_MI_BIT 16
0169 #define VER_PA_BIT 8
0170 #define VER_ID_BIT 0
0171 
0172 /*
0173  * ROUTER IDIV register fields
0174  */
0175 #define IDIV_ID (0xff << IDIV_ID_BIT)
0176 
0177 #define IDIV_ID_BIT 0
0178 
0179 /*
0180  * ROUTER CFGWE register fields
0181  */
0182 #define CFGWE_WE (0x1 << CFGWE_WE_BIT)
0183 
0184 #define CFGWE_WE_BIT 0
0185 
0186 /*
0187  * ROUTER PRESCALER register fields
0188  */
0189 #define PRESCALER_RL (0xffff << PRESCALER_RL_BIT)
0190 
0191 #define PRESCALER_RL_BIT 0
0192 
0193 /*
0194  * ROUTER IMASK register fields
0195  * DEFINED IN HEADER
0196  */
0197 
0198 /*
0199  * ROUTER ICODEGEN register fields
0200  * DEFINED IN HEADER
0201  */
0202 
0203 /*
0204  * ROUTER ISRTIMER register fields
0205  */
0206 #define ISRTIMER_RL (0xffff << ISRTIMER_RL_BIT)
0207 
0208 #define ISRTIMER_RL_BIT 0
0209 
0210 /*
0211  * ROUTER AITIMER register fields
0212  */
0213 #define AITIMER_RL (0xffff << AITIMER_RL_BIT)
0214 
0215 #define AITIMER_RL_BIT 0
0216 
0217 /*
0218  * ROUTER ISRCTIMER register fields
0219  */
0220 #define ISRCTIMER_RL (0x1f << ISRCTIMER_RL_BIT)
0221 
0222 #define ISRCTIMER_RL_BIT 0
0223 
0224 /*
0225  * ROUTER CAP register fields
0226  */
0227 #define CAP_AF (0x3 << CAP_AF_BIT)
0228 #define CAP_PF (0x7 << CAP_PF_BIT)
0229 #define CAP_RM (0x7 << CAP_RM_BIT)
0230 #define CAP_AS (0x1 << CAP_AS_BIT)
0231 #define CAP_AX (0x1 << CAP_AX_BIT)
0232 #define CAP_DP (0x1 << CAP_DP_BIT)
0233 #define CAP_ID (0x1 << CAP_ID_BIT)
0234 #define CAP_SD (0x1 << CAP_SD_BIT)
0235 #define CAP_PC (0x1f << CAP_PC_BIT)
0236 #define CAP_CC (0x1f << CAP_CC_BIT)
0237 
0238 #define CAP_AF_BIT 24
0239 #define CAP_PF_BIT 29
0240 #define CAP_RM_BIT 16
0241 #define CAP_AS_BIT 14
0242 #define CAP_AX_BIT 13
0243 #define CAP_DP_BIT 12
0244 #define CAP_ID_BIT 11
0245 #define CAP_SD_BIT 10
0246 #define CAP_PC_BIT 4
0247 #define CAP_CC_BIT 0
0248 
0249 /*
0250  * ROUTER PNPVEND register fields
0251  */
0252 #define PNPVEND_VI (0xffff << PNPVEND_VI_BIT)
0253 #define PNPVEND_PI (0xffff << PNPVEND_PI_BIT)
0254 
0255 #define PNPVEND_VI_BIT 16
0256 #define PNPVEND_PI_BIT 0
0257 
0258 /*
0259  * ROUTER PNPUVEND register fields
0260  */
0261 #define PNPUVEND_VI (0xffff << PNPUVEND_VI_BIT)
0262 #define PNPUVEND_PI (0xffff << PNPUVEND_PI_BIT)
0263 
0264 #define PNPUVEND_VI_BIT 16
0265 #define PNPUVEND_PI_BIT 0
0266 
0267 /*
0268  * ROUTER MAXPLEN register fields
0269  */
0270 #define MAXPLEN_ML (0xffffff << MAXPLEN_ML_BIT)
0271 
0272 #define MAXPLEN_ML_BIT 0
0273 
0274 /*
0275  * ROUTER CHARO register fields
0276  */
0277 #define CHARO_OR (0x1 << CHARO_OR_BIT)
0278 #define CHARO_CC (0x7fffffff << CHARO_CC_BIT)
0279 
0280 #define CHARO_OR_BIT 31
0281 #define CHARO_CC_BIT 0
0282 
0283 /*
0284  * ROUTER CHARI register fields
0285  */
0286 #define CHARI_OR (0x1 << CHARI_OR_BIT)
0287 #define CHARI_CC (0x7fffffff << CHARI_CC_BIT)
0288 
0289 #define CHARI_OR_BIT 31
0290 #define CHARI_CC_BIT 0
0291 
0292 /*
0293  * ROUTER PKTO register fields
0294  */
0295 #define PKTO_OR (0x1 << PKTO_OR_BIT)
0296 #define PKTO_CC (0x7fffffff << PKTO_CC_BIT)
0297 
0298 #define PKTO_OR_BIT 31
0299 #define PKTO_CC_BIT 0
0300 
0301 /*
0302  * ROUTER PKTI register fields
0303  */
0304 #define PKTI_OR (0x1 << PKTI_OR_BIT)
0305 #define PKTI_CC (0x7fffffff << PKTI_CC_BIT)
0306 
0307 #define PKTI_OR_BIT 31
0308 #define PKTI_CC_BIT 0
0309 
0310 /*
0311  * ROUTER CRED register fields
0312  */
0313 #define CRED_OC (0x3f << CRED_OC_BIT)
0314 #define CRED_IC (0x3f << CRED_IC_BIT)
0315 
0316 #define CRED_OC_BIT 6
0317 #define CRED_IC_BIT 0
0318 
0319 /*
0320  * ROUTER RTRCOMB register fields
0321  */
0322 #define RTRCOMB_SR (0x1 << RTRCOMB_SR_BIT)
0323 #define RTRCOMB_EN (0x1 << RTRCOMB_EN_BIT)
0324 #define RTRCOMB_PR (0x1 << RTRCOMB_PR_BIT)
0325 #define RTRCOMB_HD (0x1 << RTRCOMB_HD_BIT)
0326 #define RTRCOMB_PE (0x7ffff << RTRCOMB_PE_BIT)
0327 #define RTRCOMB_PD (0x1 << RTRCOMB_PD_BIT)
0328 
0329 #define RTRCOMB_SR_BIT 31
0330 #define RTRCOMB_EN_BIT 30
0331 #define RTRCOMB_PR_BIT 29
0332 #define RTRCOMB_HD_BIT 28
0333 #define RTRCOMB_PE_BIT 1
0334 #define RTRCOMB_PD_BIT 0
0335 
0336 struct router_regs {
0337     unsigned int resv1;     /* 0x000 */
0338     unsigned int psetup[255];   /* 0x004 */
0339     unsigned int resv2;     /* 0x400 */
0340     unsigned int routes[255];   /* 0x404 */
0341     unsigned int pctrl[32];     /* 0x800 */
0342     unsigned int psts[32];      /* 0x880 */
0343     unsigned int treload[32];   /* 0x900 */
0344     unsigned int pctrl2[32];    /* 0x980 */
0345     unsigned int cfgsts;        /* 0xA00 */
0346     unsigned int timecode;      /* 0xA04 */
0347     unsigned int ver;       /* 0xA08 */
0348     unsigned int idiv;      /* 0xA0C */
0349     unsigned int cfgwe;     /* 0xA10 */
0350     unsigned int tprescaler;    /* 0xA14 */
0351     unsigned int imask;     /* 0xA18 */
0352     unsigned int ipmask;        /* 0xA1C */
0353     unsigned int pip;       /* 0xA20 */
0354     unsigned int icodegen;      /* 0xA24 */
0355     unsigned int isr0;      /* 0xA28 */
0356     unsigned int isr1;      /* 0xA2C */
0357     unsigned int isrtimer;      /* 0xA30 */
0358     unsigned int aitimer;       /* 0xA34 */
0359     unsigned int isrctimer;     /* 0xA38 */
0360     unsigned int resv4;     /* 0xA3C */
0361     unsigned int lrunsts;       /* 0xA40 */
0362     unsigned int cap;       /* 0xA44 */
0363     unsigned int resv5[111];    /* 0xA48 */
0364     unsigned int charo[31];     /* 0xC04 */ /* TODO check GR718 */
0365     unsigned int resv6;     /* 0xC80 */
0366     unsigned int chari[31];     /* 0xC84 */
0367     unsigned int resv7;     /* 0xD00 */
0368     unsigned int pkto[31];      /* 0xD04 */
0369     unsigned int resv8;     /* 0xD80 */
0370     unsigned int pkti[31];      /* 0xD84 */
0371     unsigned int maxplen[32];       /* 0xE00 */
0372     unsigned int resv9;     /* 0xE80 */
0373     unsigned int credcnt[31];   /* 0xE84 */
0374     unsigned int resv10[64];    /* 0xF00 */
0375     unsigned int resv11;        /* 0x1000 */
0376     unsigned int rtcomb[255];   /* 0x1004 */
0377 };
0378 
0379 struct router_priv {
0380     struct drvmgr_dev *dev;
0381 
0382     /* ROUTER control registers */
0383     struct router_regs *regs;
0384 
0385     #ifdef THREAD_SAFE
0386     /* ROUTER semaphore */
0387     rtems_id sem;
0388     #endif
0389 
0390     /* ROUTER driver register */
0391     char devname[9];
0392     int index;          /* Index in order it was probed */
0393 
0394     int minor;
0395     int open;
0396     struct router_hw_info hwinfo;
0397     int nports;
0398     int irq_init;
0399 
0400     SPIN_DECLARE(plock[32])
0401 
0402 };
0403 
0404 int router_count = 0;
0405 static struct router_priv *priv_tab[ROUTER_MAX];
0406 
0407 /* Driver prototypes */
0408 
0409 STATIC int router_init(struct router_priv *priv);
0410 STATIC void router_hwinfo(struct router_priv *priv,
0411               struct router_hw_info *hwinfo);
0412 STATIC int router_acontrol_set(struct router_priv *priv,
0413         struct router_route_acontrol *control);
0414 STATIC int router_acontrol_get(struct router_priv *priv,
0415         struct router_route_acontrol *control);
0416 STATIC int router_portmap_set(struct router_priv *priv,
0417         struct router_route_portmap *pmap);
0418 STATIC int router_portmap_get(struct router_priv *priv,
0419         struct router_route_portmap *pmap);
0420 
0421 /* -IRQ handler */
0422 void router_isr(void *arg);
0423 
0424 int router_init2(struct drvmgr_dev *dev);
0425 
0426 struct drvmgr_drv_ops router_ops =
0427 {
0428     .init = {NULL,  router_init2, NULL, NULL},
0429     .remove = NULL,
0430     .info = NULL
0431 };
0432 
0433 struct amba_dev_id router_ids[] =
0434 {
0435     {VENDOR_GAISLER, GAISLER_SPW_ROUTER},
0436     {0, 0}      /* Mark end of table */
0437 };
0438 
0439 struct amba_drv_info router_drv_info =
0440 {
0441     {
0442         DRVMGR_OBJ_DRV,         /* Driver */
0443         NULL,               /* Next driver */
0444         NULL,               /* Device list */
0445         DRIVER_AMBAPP_GAISLER_SPW_ROUTER_ID,/* Driver ID */
0446         "ROUTER_DRV",           /* Driver Name */
0447         DRVMGR_BUS_TYPE_AMBAPP,     /* Bus Type */
0448         &router_ops,
0449         NULL,               /* Funcs */
0450         0,              /* No devices yet */
0451         sizeof(struct router_priv), /* Let DRVMGR allocate for us */
0452     },
0453     &router_ids[0],
0454 };
0455 
0456 void router_register_drv (void)
0457 {
0458     DBG("Registering SPW ROUTER driver\n");
0459     drvmgr_drv_register(&router_drv_info.general);
0460 }
0461 
0462 STATIC void router_hwinfo(struct router_priv *priv,
0463         struct router_hw_info *hwinfo)
0464 {
0465     unsigned int tmp;
0466 
0467     /* Find router info */
0468     tmp = REG_READ(&priv->regs->cfgsts);
0469     hwinfo->nports_spw   = (tmp & RTRCFG_SP) >> RTRCFG_SP_BIT;
0470     hwinfo->nports_amba  = (tmp & RTRCFG_AP) >> RTRCFG_AP_BIT;
0471     hwinfo->nports_fifo  = (tmp & RTRCFG_FP) >> RTRCFG_FP_BIT;
0472     hwinfo->srouting     = (tmp & RTRCFG_SR) >> RTRCFG_SR_BIT;
0473     hwinfo->pnp_enable   = (tmp & RTRCFG_PE) >> RTRCFG_PE_BIT;
0474     hwinfo->timers_avail = (tmp & RTRCFG_TA) >> RTRCFG_TA_BIT;
0475     hwinfo->pnp_avail    = (tmp & RTRCFG_PP) >> RTRCFG_PP_BIT;
0476 
0477     tmp = REG_READ(&priv->regs->ver);
0478     hwinfo->ver_major = (tmp & VER_MA) >> VER_MA_BIT;
0479     hwinfo->ver_minor = (tmp & VER_MI) >> VER_MI_BIT;
0480     hwinfo->ver_patch = (tmp & VER_PA) >> VER_PA_BIT;
0481     hwinfo->iid       = (tmp & VER_ID) >> VER_ID_BIT;
0482 
0483     /* Find router capabilities */
0484     tmp = REG_READ(&priv->regs->cap);
0485     hwinfo->amba_port_fifo_size = 4 << ((tmp & CAP_AF) >> CAP_AF_BIT);
0486     hwinfo->spw_port_fifo_size = 16 << ((tmp & CAP_PF) >> CAP_PF_BIT);
0487     hwinfo->rmap_maxdlen = 4 << ((tmp & CAP_RM) >> CAP_RM_BIT);
0488     hwinfo->aux_async = (tmp & CAP_AS) >> CAP_AS_BIT;
0489     hwinfo->aux_dist_int_support = (tmp & CAP_AX) >> CAP_AX_BIT;
0490     hwinfo->dual_port_support = (tmp & CAP_ID) >> CAP_ID_BIT;
0491     hwinfo->dist_int_support = (tmp & CAP_DP) >> CAP_DP_BIT;
0492     hwinfo->spwd_support = (tmp & CAP_SD) >> CAP_SD_BIT;
0493     hwinfo->pktcnt_support = (tmp & CAP_PC) >> CAP_PC_BIT;
0494     hwinfo->charcnt_support = (tmp & CAP_CC) >> CAP_CC_BIT;
0495 }
0496 
0497 STATIC void router_hwinfo_print(struct router_hw_info *hwinfo)
0498 {
0499     DBG(" -PORTS= SPW: %d, AMBA: %d, FIFO: %d\n", hwinfo->nports_spw,
0500             hwinfo->nports_amba, hwinfo->nports_fifo);
0501     DBG(" -Static routing: %s, Timers: %s\n",
0502             (hwinfo->srouting?"Enabled":"Disabled"),
0503             (hwinfo->timers_avail?"Available":"N/A"));
0504     DBG(" -PnP: %s, %s\n",
0505             (hwinfo->pnp_avail?"Available":"N/A"),
0506             (hwinfo->pnp_enable?"Enabled":"Disabled"));
0507     DBG(" -Version= Major: 0x%02x, Minor: 0x%02x, Patch: 0x%02x, ID: 0x%02x\n",
0508             hwinfo->ver_major, hwinfo->ver_minor,
0509             hwinfo->ver_patch, hwinfo->iid);
0510     DBG(" -Aux: %s, AuxDistInt: %s, DistInt: %s, SPWD: %s, PKTCNT: %s, "
0511         "CHARCNT: %s\n",
0512             (hwinfo->aux_async?"Async":"Sync"),
0513             (hwinfo->aux_dist_int_support?"Supported":"N/A"),
0514             (hwinfo->dist_int_support?"Supported":"N/A"),
0515             (hwinfo->spwd_support?"Supported":"N/A"),
0516             (hwinfo->pktcnt_support?"Supported":"N/A"),
0517             (hwinfo->charcnt_support?"Supported":"N/A"));
0518 }
0519 
0520 STATIC int router_acontrol_set(struct router_priv *priv,
0521         struct router_route_acontrol *control)
0522 {
0523     int i;
0524     for (i=0; i<31; i++) {
0525         REG_WRITE(&priv->regs->routes[i], control->control[i]);
0526     }
0527     for (i=0; i<224; i++) {
0528         REG_WRITE(&priv->regs->routes[i+31], control->control_logical[i]);
0529     }
0530     return ROUTER_ERR_OK;
0531 }
0532 
0533 STATIC int router_acontrol_get(struct router_priv *priv,
0534         struct router_route_acontrol *control)
0535 {
0536     int i;
0537     for (i=0; i<31; i++) {
0538         control->control[i] = REG_READ(&priv->regs->routes[i]);
0539     }
0540     for (i=0; i<224; i++) {
0541         control->control_logical[i] = REG_READ(&priv->regs->routes[i+31]);
0542     }
0543     return ROUTER_ERR_OK;
0544 }
0545 
0546 STATIC int router_portmap_set(struct router_priv *priv,
0547         struct router_route_portmap *pmap)
0548 {
0549     int i;
0550     for (i=0; i<31; i++) {
0551         REG_WRITE(&priv->regs->psetup[i], pmap->pmap[i]);
0552     }
0553     for (i=0; i<224; i++) {
0554         REG_WRITE(&priv->regs->psetup[i+31], pmap->pmap_logical[i]);
0555     }
0556     return ROUTER_ERR_OK;
0557 }
0558 
0559 STATIC int router_portmap_get(struct router_priv *priv,
0560         struct router_route_portmap *pmap)
0561 {
0562     int i;
0563     for (i=0; i<31; i++) {
0564         pmap->pmap[i] = REG_READ(&priv->regs->psetup[i]);
0565     }
0566     for (i=0; i<224; i++) {
0567         pmap->pmap_logical[i] = REG_READ(&priv->regs->psetup[i+31]);
0568     }
0569     return ROUTER_ERR_OK;
0570 }
0571 
0572 STATIC int router_init(struct router_priv *priv)
0573 {
0574     #ifdef THREAD_SAFE
0575     int i;
0576 
0577     /* Device Semaphore created with count = 1 */
0578     if (rtems_semaphore_create(
0579             rtems_build_name('S', 'R', 'O', '0' + priv->index), 1,
0580             RTEMS_FIFO | RTEMS_SIMPLE_BINARY_SEMAPHORE | \
0581             RTEMS_NO_INHERIT_PRIORITY | RTEMS_LOCAL | \
0582             RTEMS_NO_PRIORITY_CEILING, 0, &priv->sem) != RTEMS_SUCCESSFUL) {
0583         return DRVMGR_FAIL;
0584     }
0585     #endif
0586 
0587     /* Find router info */
0588     router_hwinfo(priv, &priv->hwinfo);
0589 
0590     priv->open = 0;
0591     /* Number of ports has to consider the configuration port (1 + SPW + AMBA + FIFO) */
0592     priv->nports = 1 + priv->hwinfo.nports_spw + priv->hwinfo.nports_amba +
0593         priv->hwinfo.nports_fifo;
0594     if ((priv->nports < 2) || (priv->nports > 32)) {
0595         return DRVMGR_EIO;
0596     }
0597 
0598     #ifdef THREAD_SAFE
0599     /* Init port spin-lock memory structures */
0600     for (i=0; i<priv->nports; i++) {
0601         SPIN_INIT(&priv->plock[i],"portlock");
0602     }
0603     #endif
0604 
0605     /* DEBUG print */
0606     DBG("SPW ROUTER[%d] with following capabilities:\n", priv->index);
0607     router_hwinfo_print(&priv->hwinfo);
0608 
0609     return DRVMGR_OK;
0610 }
0611 
0612 int router_init2(struct drvmgr_dev *dev)
0613 {
0614     struct router_priv *priv = dev->priv;
0615     struct amba_dev_info *ambadev;
0616     struct ambapp_core *pnpinfo;
0617     unsigned int tmp;
0618     int i;
0619     int status;
0620 
0621     DBG("SPW ROUTER[%d] on bus %s\n", dev->minor_drv, dev->parent->dev->name);
0622 
0623     if (router_count >= ROUTER_MAX) {
0624         return DRVMGR_ENORES;
0625     }
0626 
0627     if (priv == NULL) {
0628         return DRVMGR_NOMEM;
0629     }
0630     priv->dev = dev;
0631 
0632     /* Get device information from AMBA PnP information */
0633     ambadev = (struct amba_dev_info *)priv->dev->businfo;
0634     if (ambadev == NULL) {
0635         return DRVMGR_FAIL;
0636     }
0637     pnpinfo = &ambadev->info;
0638     priv->regs = (struct router_regs *)pnpinfo->ahb_slv->start[0];
0639     priv->minor = dev->minor_drv;
0640 
0641     /* Initilize driver struct */
0642     status = router_init(priv);
0643     if (status != DRVMGR_OK) {
0644         return status;
0645     }
0646 
0647     /* Startup Action:
0648      *  - Clear interrupts
0649      *  - Mask interrupts
0650      */
0651 
0652     /* Mask interrupts in ROTUER */
0653     REG_WRITE(&priv->regs->imask,0);
0654     REG_WRITE(&priv->regs->ipmask,0);
0655 
0656     /* Clear interrupts in ROTUER */
0657     REG_WRITE(&priv->regs->pip,0xffffffff);
0658 
0659     /* Clear errors in router and ports */
0660     tmp = REG_READ(&priv->regs->cfgsts);
0661     REG_WRITE(&priv->regs->cfgsts, tmp | RTRCFG_WCLEAR);
0662     tmp = REG_READ(&priv->regs->psts[0]);
0663     REG_WRITE(&priv->regs->psts[0], (tmp & PSTSCFG_WCLEAR) | PSTSCFG_WCLEAR2);
0664     for (i=1; i<priv->nports; i++) {
0665         tmp = REG_READ(&priv->regs->psts[i]);
0666         REG_WRITE(&priv->regs->psts[i], tmp & PSTS_WCLEAR);
0667     }
0668 
0669     /* Register driver internally */
0670     priv->index = router_count;
0671     priv_tab[priv->index] = priv;
0672     router_count++;
0673 
0674     /* Device name */
0675     sprintf(priv->devname, "router%d", priv->index);
0676 
0677     return DRVMGR_OK;
0678 }
0679 
0680 void *router_open(unsigned int dev_no)
0681 {
0682     struct router_priv *priv, *ret;
0683 
0684     if (dev_no >= router_count) {
0685         DBG("ROUTER Wrong index %u\n", dev_no);
0686         return NULL;
0687     }
0688 
0689     priv = priv_tab[dev_no];
0690 
0691     if (priv == NULL) {
0692         DBG("ROUTER Device not initialized\n");
0693         return NULL;
0694     }
0695 
0696     #ifdef THREAD_SAFE
0697     /* Take device lock - Wait until we get semaphore */
0698     if (rtems_semaphore_obtain(priv->sem, RTEMS_WAIT, RTEMS_NO_TIMEOUT)
0699             != RTEMS_SUCCESSFUL) {
0700         DBG("ROUTER Sempahore failed\n");
0701         return NULL;
0702     }
0703     #endif
0704 
0705     if (priv->open) {
0706         DBG("ROUTER Device already opened\n");
0707         ret = NULL;
0708     } else {
0709         /* Take the device */
0710         priv->open = 1;
0711         ret = priv;
0712     }
0713     #ifdef THREAD_SAFE
0714     /* Unlock dev */
0715     rtems_semaphore_release(priv->sem);
0716     #endif
0717 
0718     return ret;
0719 }
0720 
0721 int router_close(void *d)
0722 {
0723     struct router_priv *priv = d;
0724     int ret;
0725 
0726     if (priv == NULL) {
0727         DBG("ROUTER Device not initialized\n");
0728         return ROUTER_ERR_EINVAL;
0729     }
0730 
0731     #ifdef THREAD_SAFE
0732     /* Take device lock - Wait until we get semaphore */
0733     if (rtems_semaphore_obtain(priv->sem, RTEMS_WAIT, RTEMS_NO_TIMEOUT)
0734             != RTEMS_SUCCESSFUL) {
0735         DBG("ROUTER Sempahore failed\n");
0736         return ROUTER_ERR_ERROR;
0737     }
0738     #endif
0739 
0740     if (priv->open == 0) {
0741         DBG("ROUTER Device already closed\n");
0742         ret = ROUTER_ERR_ERROR;
0743     } else {
0744         /* Mark not open */
0745         priv->open = 0;
0746         ret = ROUTER_ERR_OK;
0747     }
0748 
0749     #ifdef THREAD_SAFE
0750     /* Unlock dev */
0751     rtems_semaphore_release(priv->sem);
0752     #endif
0753 
0754     return ret;
0755 }
0756 
0757 STATIC int router_check_open(void *d)
0758 {
0759     struct router_priv *priv = d;
0760 
0761     if (priv == NULL) {
0762         DBG("ROUTER Device not initialized\n");
0763         return ROUTER_ERR_EINVAL;
0764     }
0765 
0766     if (priv->open == 0) {
0767         DBG("ROUTER Device closed\n");
0768         return ROUTER_ERR_ERROR;
0769     }
0770 
0771     return 0;
0772 }
0773 
0774 STATIC int router_check_port(void *d, int port)
0775 {
0776     int ret = router_check_open(d);
0777 
0778     if (ret == 0) {
0779         struct router_priv *priv = d;
0780         if((port < 0) || (port >= priv->nports)) {
0781             DBG("ROUTER wrong port\n");
0782             ret = ROUTER_ERR_EINVAL;
0783         }
0784     }
0785 
0786     return ret;
0787 }
0788 
0789 STATIC int router_check_distint_support(void *d)
0790 {
0791     int ret = router_check_open(d);
0792 
0793     if (ret == 0) {
0794         struct router_priv *priv = d;
0795         if (priv->hwinfo.dist_int_support == 0) {
0796             DBG("ROUTER Dist interrupts not supported\n");
0797             ret = ROUTER_ERR_IMPLEMENTED;
0798         }
0799     }
0800 
0801     return ret;
0802 }
0803 
0804 int router_hwinfo_get(void *d, struct router_hw_info *hwinfo)
0805 {
0806     struct router_priv *priv = d;
0807     int error = router_check_open(d);
0808 
0809     if (error)
0810         return error;
0811 
0812     if (hwinfo == NULL) {
0813         DBG("ROUTER Wrong pointer\n");
0814         return ROUTER_ERR_EINVAL;
0815     }
0816 
0817     /* Get hwinfo */
0818     router_hwinfo(priv, hwinfo);
0819 
0820     return ROUTER_ERR_OK;
0821 }
0822 
0823 int router_print(void *d)
0824 {
0825     struct router_priv *priv = d;
0826     int error = router_check_open(d);
0827 
0828     if (error)
0829         return error;
0830 
0831     /* DEBUG print */
0832     DBG("Number of routers: %d\n", router_count);
0833     DBG("SPW ROUTER[%d] with following capabilities:\n", priv->index);
0834     router_hwinfo_print(&priv->hwinfo);
0835 
0836     return ROUTER_ERR_OK;
0837 }
0838 
0839 /* Configure Router. Leave field NULL in order to skip configuration
0840  */
0841 int router_config_set(void *d, struct router_config *cfg)
0842 {
0843     struct router_priv *priv = d;
0844     int error = router_check_open(d);
0845 
0846     if (error)
0847         return error;
0848 
0849     if (cfg == NULL) {
0850         DBG("ROUTER CFG wrong\n");
0851         return ROUTER_ERR_EINVAL;
0852     }
0853 
0854     if ((cfg->flags & (ROUTER_FLG_TPRES|ROUTER_FLG_TRLD)) &&
0855             !priv->hwinfo.timers_avail) {
0856         return ROUTER_ERR_IMPLEMENTED;
0857     }
0858 
0859     #ifdef THREAD_SAFE
0860     /* Take device lock - Wait until we get semaphore */
0861     if (rtems_semaphore_obtain(priv->sem, RTEMS_WAIT, RTEMS_NO_TIMEOUT)
0862             != RTEMS_SUCCESSFUL) {
0863         DBG("ROUTER Sempahore failed\n");
0864         return ROUTER_ERR_ERROR;
0865     }
0866     #endif
0867 
0868     /* Write only configuration bits in Config register */
0869     if (cfg->flags & ROUTER_FLG_CFG) {
0870         REG_WRITE(&priv->regs->cfgsts, cfg->config & ~(RTRCFG_WCLEAR));
0871     }
0872 
0873     /* Write Instance ID to Version Register */
0874     if (cfg->flags & ROUTER_FLG_IID) {
0875         REG_WRITE(&priv->regs->ver, (cfg->iid << VER_ID_BIT) & VER_ID);
0876     }
0877 
0878     /* Write startup-clock-divisor Register */
0879     if (cfg->flags & ROUTER_FLG_IDIV) {
0880         REG_WRITE(&priv->regs->idiv, (cfg->idiv << IDIV_ID_BIT) & IDIV_ID);
0881     }
0882 
0883     /* Write Timer Prescaler Register */
0884     if (cfg->flags & ROUTER_FLG_TPRES) {
0885         REG_WRITE(&priv->regs->tprescaler,
0886                 (cfg->timer_prescaler << PRESCALER_RL_BIT) & PRESCALER_RL);
0887     }
0888 
0889     #ifdef THREAD_SAFE
0890     /* Unlock dev */
0891     rtems_semaphore_release(priv->sem);
0892     #endif
0893 
0894     return ROUTER_ERR_OK;
0895 }
0896 
0897 int router_config_get(void *d, struct router_config *cfg)
0898 {
0899     struct router_priv *priv = d;
0900     int error = router_check_open(d);
0901 
0902     if (error)
0903         return error;
0904 
0905     if (cfg == NULL) {
0906         DBG("ROUTER CFG wrong\n");
0907         return ROUTER_ERR_EINVAL;
0908     }
0909 
0910     #ifdef THREAD_SAFE
0911     /* Take device lock - Wait until we get semaphore */
0912     if (rtems_semaphore_obtain(priv->sem, RTEMS_WAIT, RTEMS_NO_TIMEOUT)
0913             != RTEMS_SUCCESSFUL) {
0914         DBG("ROUTER Sempahore failed\n");
0915         return ROUTER_ERR_ERROR;
0916     }
0917     #endif
0918 
0919     cfg->config = REG_READ(&priv->regs->cfgsts) &
0920         ~(RTRCFG_SP|RTRCFG_AP|RTRCFG_FP|RTRCFG_SR|RTRCFG_PE|RTRCFG_ME|
0921           RTRCFG_TA|RTRCFG_PP);
0922     cfg->iid = (REG_READ(&priv->regs->ver) & VER_ID) >> VER_ID_BIT;
0923     cfg->idiv = (REG_READ(&priv->regs->idiv) & IDIV_ID) >> IDIV_ID_BIT;
0924     cfg->timer_prescaler =
0925         (REG_READ(&priv->regs->tprescaler) & PRESCALER_RL) >> PRESCALER_RL_BIT;
0926 
0927     #ifdef THREAD_SAFE
0928     /* Unlock dev */
0929     rtems_semaphore_release(priv->sem);
0930     #endif
0931 
0932     return ROUTER_ERR_OK;
0933 }
0934 
0935 /* Configure Router routing table.
0936  * Leave field NULL in order to skip configuration
0937  */
0938 int router_routing_table_set(void *d, struct router_routing_table *cfg)
0939 {
0940     struct router_priv *priv = d;
0941     int error = router_check_open(d);
0942 
0943     if (error)
0944         return error;
0945 
0946     if (cfg == NULL) {
0947         DBG("ROUTER CFG wrong\n");
0948         return ROUTER_ERR_EINVAL;
0949     }
0950 
0951     #ifdef THREAD_SAFE
0952     /* Take device lock - Wait until we get semaphore */
0953     if (rtems_semaphore_obtain(priv->sem, RTEMS_WAIT, RTEMS_NO_TIMEOUT)
0954             != RTEMS_SUCCESSFUL) {
0955         DBG("ROUTER Sempahore failed\n");
0956         return ROUTER_ERR_ERROR;
0957     }
0958     #endif
0959 
0960     /* Write Address control */
0961     if (cfg->flags & ROUTER_ROUTE_FLG_CTRL) {
0962         router_acontrol_set(priv,&cfg->acontrol);
0963     }
0964 
0965     /* Write Port map */
0966     if (cfg->flags & ROUTER_ROUTE_FLG_MAP) {
0967         router_portmap_set(priv,&cfg->portmap);
0968     }
0969 
0970     #ifdef THREAD_SAFE
0971     /* Unlock dev */
0972     rtems_semaphore_release(priv->sem);
0973     #endif
0974 
0975     return ROUTER_ERR_OK;
0976 }
0977 
0978 int router_routing_table_get(void *d, struct router_routing_table *cfg)
0979 {
0980     struct router_priv *priv = d;
0981     int error = router_check_open(d);
0982 
0983     if (error)
0984         return error;
0985 
0986     if (cfg == NULL) {
0987         DBG("ROUTER CFG wrong\n");
0988         return ROUTER_ERR_EINVAL;
0989     }
0990 
0991     #ifdef THREAD_SAFE
0992     /* Take device lock - Wait until we get semaphore */
0993     if (rtems_semaphore_obtain(priv->sem, RTEMS_WAIT, RTEMS_NO_TIMEOUT)
0994             != RTEMS_SUCCESSFUL) {
0995         DBG("ROUTER Sempahore failed\n");
0996         return ROUTER_ERR_ERROR;
0997     }
0998     #endif
0999 
1000     /* Read Address control */
1001     router_acontrol_get(priv,&cfg->acontrol);
1002 
1003     /* Read Port map */
1004     router_portmap_get(priv,&cfg->portmap);
1005 
1006     #ifdef THREAD_SAFE
1007     /* Unlock dev */
1008     rtems_semaphore_release(priv->sem);
1009     #endif
1010 
1011     return ROUTER_ERR_OK;
1012 }
1013 
1014 int router_route_set(void *d, struct router_route *route)
1015 {
1016     struct router_priv *priv = d;
1017     int i;
1018     unsigned int mask;
1019     int error = router_check_open(d);
1020 
1021     if (error)
1022         return error;
1023 
1024     if (route == NULL) {
1025         DBG("ROUTER route wrong\n");
1026         return ROUTER_ERR_EINVAL;
1027     }
1028 
1029     if (route->from_address < 32) {
1030         /* Physical address */
1031         if ((route->from_address == 0) ||
1032                 (route->from_address >= priv->nports)) {
1033             DBG("ROUTER wrong physical address\n");
1034             return ROUTER_ERR_TOOMANY;
1035         }
1036     }
1037 
1038     /* Compute port map */
1039     mask=0;
1040     for (i=0; i < route->count; i++) {
1041         if ((route->to_port[i] == 0) || (route->to_port[i] >= priv->nports)) {
1042             DBG("ROUTER route wrong destiny port\n");
1043             return ROUTER_ERR_EINVAL;
1044         }
1045         mask |= (0x1 << route->to_port[i]);
1046     }
1047     if (route->options & ROUTER_ROUTE_PACKETDISTRIBUTION_ENABLE) {
1048         mask |= RTPMAP_PD;
1049     }
1050 
1051     #ifdef THREAD_SAFE
1052     /* Take device lock - Wait until we get semaphore */
1053     if (rtems_semaphore_obtain(priv->sem, RTEMS_WAIT, RTEMS_NO_TIMEOUT)
1054             != RTEMS_SUCCESSFUL) {
1055         DBG("ROUTER Sempahore failed\n");
1056         return ROUTER_ERR_ERROR;
1057     }
1058     #endif
1059 
1060     /* Write port map */
1061     REG_WRITE(&priv->regs->psetup[route->from_address-1], mask);
1062 
1063     /* Write Address control */
1064     REG_WRITE(&priv->regs->routes[route->from_address-1],
1065             route->options & (0xf));
1066 
1067     #ifdef THREAD_SAFE
1068     /* Unlock dev */
1069     rtems_semaphore_release(priv->sem);
1070     #endif
1071 
1072     return ROUTER_ERR_OK;
1073 }
1074 
1075 int router_route_get(void *d, struct router_route *route)
1076 {
1077     struct router_priv *priv = d;
1078     int i,count;
1079     unsigned int mask;
1080     int error = router_check_open(d);
1081 
1082     if (error)
1083         return error;
1084 
1085     if (route == NULL) {
1086         DBG("ROUTER route wrong\n");
1087         return ROUTER_ERR_EINVAL;
1088     }
1089 
1090     if (route->from_address < 32) {
1091         /* Physical address */
1092         if ((route->from_address == 0) ||
1093                 (route->from_address >= priv->nports)) {
1094             DBG("ROUTER wrong physical address\n");
1095             return ROUTER_ERR_TOOMANY;
1096         }
1097     }
1098 
1099     #ifdef THREAD_SAFE
1100     /* Take device lock - Wait until we get semaphore */
1101     if (rtems_semaphore_obtain(priv->sem, RTEMS_WAIT, RTEMS_NO_TIMEOUT)
1102             != RTEMS_SUCCESSFUL) {
1103         DBG("ROUTER Sempahore failed\n");
1104         return ROUTER_ERR_ERROR;
1105     }
1106     #endif
1107 
1108     /* Get Address control */
1109     route->options =
1110         REG_READ(&priv->regs->routes[route->from_address-1]) & (0xf);
1111 
1112     /* Read port map */
1113     mask=REG_READ(&priv->regs->psetup[route->from_address-1]);
1114 
1115     #ifdef THREAD_SAFE
1116     /* Unlock dev */
1117     rtems_semaphore_release(priv->sem);
1118     #endif
1119 
1120     if (mask & RTPMAP_PD) {
1121         route->options |= ROUTER_ROUTE_PACKETDISTRIBUTION_ENABLE;
1122     }
1123 
1124     /*DBG("ROUTE from address 0x%02x read, PMAP: 0x%08x, CTRL: 0x%08x\n",
1125      *      (unsigned int) route->from_address, mask,
1126      *      (unsigned int) route->options);*/
1127 
1128     i=0;
1129     count=0;
1130     mask &= (RTPMAP_PE);
1131     while (mask != 0) {
1132         if (mask & 0x1) {
1133             route->to_port[count] = i;
1134             count++;
1135         }
1136         mask >>= 1;
1137         i++;
1138     }
1139     route->count=count;
1140 
1141     return ROUTER_ERR_OK;
1142 }
1143 
1144 int router_write_enable(void *d)
1145 {
1146     struct router_priv *priv = d;
1147     int error = router_check_open(d);
1148 
1149     if (error)
1150         return error;
1151 
1152     REG_WRITE(&priv->regs->cfgwe, 0x1);
1153 
1154     return ROUTER_ERR_OK;
1155 }
1156 
1157 int router_write_disable(void *d)
1158 {
1159     struct router_priv *priv = d;
1160     int error = router_check_open(d);
1161 
1162     if (error)
1163         return error;
1164 
1165     REG_WRITE(&priv->regs->cfgwe, 0x0);
1166 
1167     return ROUTER_ERR_OK;
1168 }
1169 
1170 int router_port_ioc(void *d, int port, struct router_port *cfg)
1171 {
1172     struct router_priv *priv = d;
1173     unsigned int ctrl, ctrl2, sts, timer, pktl;
1174     SPIN_IRQFLAGS(irqflags);
1175     int error = router_check_port(d, port);
1176 
1177     if (error)
1178         return error;
1179 
1180     if (cfg == NULL) {
1181         DBG("ROUTER Wrong cfg\n");
1182         return ROUTER_ERR_EINVAL;
1183     }
1184 
1185     SPIN_LOCK_IRQ(&priv->plock[port], irqflags);
1186 
1187     ctrl = cfg->ctrl;
1188     if (cfg->flag & ROUTER_PORT_FLG_GET_CTRL) {
1189         ctrl = REG_READ(&priv->regs->pctrl[port]);
1190     }
1191     ctrl2 = cfg->ctrl;
1192     if (cfg->flag & ROUTER_PORT_FLG_GET_CTRL2) {
1193         ctrl2 = REG_READ(&priv->regs->pctrl2[port]);
1194     }
1195     sts = cfg->sts;
1196     if (cfg->flag & ROUTER_PORT_FLG_GET_STS) {
1197         sts = REG_READ(&priv->regs->psts[port]);
1198     }
1199     timer = cfg->timer_reload;
1200     if (cfg->flag & ROUTER_PORT_FLG_GET_TIMER) {
1201         REG_READ(&priv->regs->treload[port]);
1202     }
1203     pktl = cfg->packet_length;
1204     if (cfg->flag & ROUTER_PORT_FLG_GET_PKTLEN) {
1205         REG_READ(&priv->regs->maxplen[port]);
1206     }
1207 
1208     if (cfg->flag & ROUTER_PORT_FLG_SET_CTRL) {
1209         REG_WRITE(&priv->regs->pctrl[port], cfg->ctrl);
1210     }
1211     if (cfg->flag & ROUTER_PORT_FLG_SET_CTRL2) {
1212         REG_WRITE(&priv->regs->pctrl2[port], cfg->ctrl2);
1213     }
1214     if (cfg->flag & ROUTER_PORT_FLG_SET_STS) {
1215         REG_WRITE(&priv->regs->psts[port], cfg->sts);
1216     }
1217     if (cfg->flag & ROUTER_PORT_FLG_SET_TIMER) {
1218         REG_WRITE(&priv->regs->treload[port], cfg->timer_reload & PTIMER_RL);
1219     }
1220     if (cfg->flag & ROUTER_PORT_FLG_SET_PKTLEN) {
1221         REG_WRITE(&priv->regs->maxplen[port], cfg->packet_length & MAXPLEN_ML);
1222     }
1223 
1224     SPIN_UNLOCK_IRQ(&priv->plock[port], irqflags);
1225 
1226     cfg->ctrl = ctrl;
1227     cfg->ctrl2 = ctrl2;
1228     cfg->sts = sts;
1229     cfg->timer_reload = timer;
1230     cfg->packet_length = pktl;
1231 
1232     return ROUTER_ERR_OK;
1233 }
1234 
1235 int router_port_ctrl_rmw(void *d, int port, uint32_t *oldvalue, uint32_t bitmask, uint32_t value)
1236 {
1237     struct router_priv *priv = d;
1238     int error = router_check_port(d, port);
1239     unsigned int oldctrl, ctrl;
1240     SPIN_IRQFLAGS(irqflags);
1241 
1242     if (error)
1243         return error;
1244 
1245     SPIN_LOCK_IRQ(&priv->plock[port], irqflags);
1246 
1247     oldctrl = REG_READ(&priv->regs->pctrl[port]);
1248     ctrl = ((oldctrl & ~(bitmask)) | (value & bitmask));
1249     REG_WRITE(&priv->regs->pctrl[port], ctrl);
1250 
1251     SPIN_UNLOCK_IRQ(&priv->plock[port], irqflags);
1252 
1253     if (oldvalue != NULL) {
1254         *oldvalue = oldctrl;
1255     }
1256 
1257     return ROUTER_ERR_OK;
1258 }
1259 
1260 int router_port_ctrl2_rmw(void *d, int port, uint32_t *oldvalue, uint32_t bitmask, uint32_t value)
1261 {
1262     struct router_priv *priv = d;
1263     int error = router_check_port(d, port);
1264     unsigned int oldctrl, ctrl;
1265     SPIN_IRQFLAGS(irqflags);
1266 
1267     if (error)
1268         return error;
1269 
1270     SPIN_LOCK_IRQ(&priv->plock[port], irqflags);
1271 
1272     oldctrl = REG_READ(&priv->regs->pctrl2[port]);
1273     ctrl = ((oldctrl & ~(bitmask)) | (value & bitmask));
1274     REG_WRITE(&priv->regs->pctrl2[port], ctrl);
1275 
1276     SPIN_UNLOCK_IRQ(&priv->plock[port], irqflags);
1277 
1278     if (oldvalue != NULL) {
1279         *oldvalue = oldctrl;
1280     }
1281 
1282     return ROUTER_ERR_OK;
1283 }
1284 
1285 /* Read Port Control register */
1286 int router_port_ctrl_get(void *d, int port, uint32_t *ctrl)
1287 {
1288     struct router_priv *priv = d;
1289     int error = router_check_port(d, port);
1290 
1291     if (error)
1292         return error;
1293 
1294     if (ctrl == NULL) {
1295         DBG("ROUTER Wrong ctrl\n");
1296         return ROUTER_ERR_EINVAL;
1297     }
1298 
1299     *ctrl = REG_READ(&priv->regs->pctrl[port]);
1300     return ROUTER_ERR_OK;
1301 }
1302 
1303 /* Read Port Status register and clear errors if there are */
1304 int router_port_status(void *d, int port, uint32_t *sts, uint32_t clrmsk)
1305 {
1306     struct router_priv *priv = d;
1307     int error = router_check_port(d, port);
1308     SPIN_IRQFLAGS(irqflags);
1309 
1310     if (error)
1311         return error;
1312 
1313     if (sts == NULL) {
1314         DBG("ROUTER Wrong sts\n");
1315         return ROUTER_ERR_EINVAL;
1316     }
1317 
1318     SPIN_LOCK_IRQ(&priv->plock[port], irqflags);
1319     *sts = REG_READ(&priv->regs->psts[port]);
1320     if (port == 0) {
1321         REG_WRITE(&priv->regs->psts[port], ((*sts) & (PSTSCFG_WCLEAR & clrmsk)) | (PSTSCFG_WCLEAR2 & clrmsk));
1322     }else{
1323         REG_WRITE(&priv->regs->psts[port], (*sts) & (PSTS_WCLEAR & clrmsk));
1324     }
1325     SPIN_UNLOCK_IRQ(&priv->plock[port], irqflags);
1326     return ROUTER_ERR_OK;
1327 }
1328 
1329 /* Read Port Control2 register */
1330 int router_port_ctrl2_get(void *d, int port, uint32_t *ctrl2)
1331 {
1332     struct router_priv *priv = d;
1333     int error = router_check_port(d, port);
1334 
1335     if (error)
1336         return error;
1337 
1338     if (ctrl2 == NULL) {
1339         DBG("ROUTER Wrong ctrl2\n");
1340         return ROUTER_ERR_EINVAL;
1341     }
1342 
1343     *ctrl2 = REG_READ(&priv->regs->pctrl2[port]);
1344     return ROUTER_ERR_OK;
1345 }
1346 
1347 /* Write Port Control Register */
1348 int router_port_ctrl_set(void *d, int port, uint32_t mask, uint32_t ctrl)
1349 {
1350     return router_port_ctrl_rmw(d, port, NULL, mask, ctrl);
1351 }
1352 
1353 /* Write Port Control2 Register */
1354 int router_port_ctrl2_set(void *d, int port, uint32_t mask, uint32_t ctrl2)
1355 {
1356     return router_port_ctrl_rmw(d, port, NULL, mask, ctrl2);
1357 }
1358 
1359 int router_port_treload_set(void *d, int port, uint32_t reload)
1360 {
1361     struct router_priv *priv = d;
1362     int error = router_check_port(d, port);
1363 
1364     if (error)
1365         return error;
1366 
1367     REG_WRITE(&priv->regs->treload[port], reload & PTIMER_RL);
1368 
1369     return ROUTER_ERR_OK;
1370 }
1371 
1372 int router_port_treload_get(void *d, int port, uint32_t *reload)
1373 {
1374     struct router_priv *priv = d;
1375     int error = router_check_port(d, port);
1376 
1377     if (error)
1378         return error;
1379 
1380     if (reload == NULL) {
1381         DBG("ROUTER Wrong reload pointer\n");
1382         return ROUTER_ERR_EINVAL;
1383     }
1384 
1385     *reload = REG_READ(&priv->regs->treload[port]) & PTIMER_RL;
1386 
1387     return ROUTER_ERR_OK;
1388 }
1389 
1390 int router_port_maxplen_set(void *d, int port, uint32_t length)
1391 {
1392     struct router_priv *priv = d;
1393     int error = router_check_port(d, port);
1394 
1395     if (error)
1396         return error;
1397 
1398     REG_WRITE(&priv->regs->maxplen[port], length & MAXPLEN_ML);
1399 
1400     return ROUTER_ERR_OK;
1401 }
1402 
1403 int router_port_maxplen_get(void *d, int port, uint32_t *length)
1404 {
1405     struct router_priv *priv = d;
1406     int error = router_check_port(d, port);
1407 
1408     if (error)
1409         return error;
1410 
1411     if (length == NULL) {
1412         DBG("ROUTER Wrong length pointer\n");
1413         return ROUTER_ERR_EINVAL;
1414     }
1415 
1416     *length = REG_READ(&priv->regs->maxplen[port]);
1417 
1418     return ROUTER_ERR_OK;
1419 }
1420 
1421 /* Get Port Link Status */
1422 int router_port_link_status(void *d, int port)
1423 {
1424     struct router_priv *priv = d;
1425     int error = router_check_port(d, port);
1426 
1427     if (error)
1428         return error;
1429 
1430     return ((REG_READ(&priv->regs->psts[port]) & PSTS_LS) >> PSTS_LS_BIT);
1431 }
1432 
1433 int router_port_disable(void *d, int port)
1434 {
1435     return router_port_ctrl_rmw(d, port, NULL, PCTRL_DI, PCTRL_DI);
1436 }
1437 
1438 int router_port_enable(void *d, int port)
1439 {
1440     return router_port_ctrl_rmw(d, port, NULL, PCTRL_DI, 0);
1441 }
1442 
1443 int router_port_link_stop(void *d, int port)
1444 {
1445     return router_port_ctrl_rmw(d, port, NULL, PCTRL_LD | PCTRL_LS, PCTRL_LD);
1446 }
1447 
1448 int router_port_link_start(void *d, int port)
1449 {
1450     return router_port_ctrl_rmw(d, port, NULL, PCTRL_LD | PCTRL_LS, PCTRL_LS);
1451 }
1452 
1453 int router_port_link_div(void *d, int port, int rundiv)
1454 {
1455     return router_port_ctrl_rmw(d, port, NULL, PCTRL_RD, (rundiv << PCTRL_RD_BIT) & PCTRL_RD);
1456 }
1457 
1458 int router_port_link_receive_spill(void *d, int port)
1459 {
1460     struct router_priv *priv = d;
1461     unsigned int ctrl;
1462     SPIN_IRQFLAGS(irqflags);
1463     int error = router_check_port(d, port);
1464 
1465     if (error)
1466         return error;
1467 
1468     SPIN_LOCK_IRQ(&priv->plock[port], irqflags);
1469 
1470     ctrl = REG_READ(&priv->regs->pctrl[port]);
1471     REG_WRITE(&priv->regs->pctrl[port], (ctrl| (PCTRL_RS)));
1472 
1473     /* Wait until the spill is done */
1474     while(REG_READ(&priv->regs->pctrl[port]) & PCTRL_RS) {};
1475 
1476     SPIN_UNLOCK_IRQ(&priv->plock[port], irqflags);
1477 
1478     return ROUTER_ERR_OK;
1479 }
1480 
1481 int router_port_link_transmit_reset(void *d, int port)
1482 {
1483     struct router_priv *priv = d;
1484     unsigned int ctrl;
1485     SPIN_IRQFLAGS(irqflags);
1486     int error = router_check_port(d, port);
1487 
1488     if (error)
1489         return error;
1490 
1491     SPIN_LOCK_IRQ(&priv->plock[port], irqflags);
1492 
1493     ctrl = REG_READ(&priv->regs->pctrl[port]);
1494     REG_WRITE(&priv->regs->pctrl[port], (ctrl| (PCTRL_TF)));
1495 
1496     /* Wait until the spill is done */
1497     while(REG_READ(&priv->regs->pctrl[port]) & PCTRL_TF) {};
1498 
1499     SPIN_UNLOCK_IRQ(&priv->plock[port], irqflags);
1500 
1501     return ROUTER_ERR_OK;
1502 }
1503 
1504 int router_port_cred_get(void *d, int port, uint32_t *cred)
1505 {
1506     struct router_priv *priv = d;
1507     int error = router_check_port(d, port);
1508 
1509     if (error)
1510         return error;
1511 
1512     if (cred == NULL) {
1513         DBG("ROUTER Wrong cred pointer\n");
1514         return ROUTER_ERR_EINVAL;
1515     }
1516 
1517     *cred = REG_READ(&priv->regs->credcnt[port]);
1518     return ROUTER_ERR_OK;
1519 }
1520 
1521 int router_instance_set(void *d, uint8_t instance)
1522 {
1523     struct router_priv *priv = d;
1524     int error = router_check_open(d);
1525 
1526     if (error)
1527         return error;
1528 
1529     REG_WRITE(&priv->regs->ver, (instance << VER_ID_BIT) & VER_ID);
1530     return ROUTER_ERR_OK;
1531 }
1532 
1533 int router_idiv_set(void *d, uint8_t idiv)
1534 {
1535     struct router_priv *priv = d;
1536     int error = router_check_open(d);
1537 
1538     if (error)
1539         return error;
1540 
1541     REG_WRITE(&priv->regs->idiv, (idiv << IDIV_ID_BIT) & IDIV_ID);
1542     return ROUTER_ERR_OK;
1543 }
1544 
1545 int router_tpresc_set(void *d, uint32_t prescaler)
1546 {
1547     struct router_priv *priv = d;
1548     int error = router_check_open(d);
1549 
1550     if (error)
1551         return error;
1552 
1553     REG_WRITE(&priv->regs->tprescaler,
1554             (prescaler << PRESCALER_RL_BIT) & PRESCALER_RL);
1555     return ROUTER_ERR_OK;
1556 }
1557 
1558 int router_instance_get(void *d, uint8_t *instance)
1559 {
1560     struct router_priv *priv = d;
1561     int error = router_check_open(d);
1562 
1563     if (error)
1564         return error;
1565 
1566     if (instance == NULL) {
1567         DBG("ROUTER Wrong instance pointer\n");
1568         return ROUTER_ERR_EINVAL;
1569     }
1570 
1571     *instance = REG_READ(&priv->regs->ver);
1572 
1573     return ROUTER_ERR_OK;
1574 }
1575 
1576 int router_idiv_get(void *d, uint8_t *idiv)
1577 {
1578     struct router_priv *priv = d;
1579     int error = router_check_open(d);
1580 
1581     if (error)
1582         return error;
1583 
1584     if (idiv == NULL) {
1585         DBG("ROUTER Wrong idiv pointer\n");
1586         return ROUTER_ERR_EINVAL;
1587     }
1588 
1589     *idiv = REG_READ(&priv->regs->idiv);
1590 
1591     return ROUTER_ERR_OK;
1592 }
1593 
1594 int router_tpresc_get(void *d, uint32_t *prescaler)
1595 {
1596     struct router_priv *priv = d;
1597     int error = router_check_open(d);
1598 
1599     if (error)
1600         return error;
1601 
1602     if (prescaler == NULL) {
1603         DBG("ROUTER Wrong prescaler pointer\n");
1604         return ROUTER_ERR_EINVAL;
1605     }
1606 
1607     *prescaler = REG_READ(&priv->regs->tprescaler);
1608 
1609     return ROUTER_ERR_OK;
1610 }
1611 
1612 int router_cfgsts_set(void *d, uint32_t cfgsts)
1613 {
1614     struct router_priv *priv = d;
1615     int error = router_check_open(d);
1616 
1617     if (error)
1618         return error;
1619 
1620     REG_WRITE(&priv->regs->cfgsts, cfgsts);
1621 
1622     return ROUTER_ERR_OK;
1623 }
1624 
1625 int router_cfgsts_get(void *d, uint32_t *cfgsts)
1626 {
1627     struct router_priv *priv = d;
1628     int error = router_check_open(d);
1629 
1630     if (error)
1631         return error;
1632 
1633     if (cfgsts == NULL) {
1634         DBG("ROUTER Wrong cfgsts pointer\n");
1635         return ROUTER_ERR_EINVAL;
1636     }
1637 
1638     *cfgsts = REG_READ(&priv->regs->cfgsts);
1639 
1640     return ROUTER_ERR_OK;
1641 }
1642 
1643 int router_tc_enable(void *d)
1644 {
1645     struct router_priv *priv = d;
1646     int error = router_check_open(d);
1647 
1648     if (error)
1649         return error;
1650 
1651     REG_WRITE(&priv->regs->timecode, TC_EN);
1652 
1653     return ROUTER_ERR_OK;
1654 }
1655 
1656 int router_tc_disable(void *d)
1657 {
1658     struct router_priv *priv = d;
1659     int error = router_check_open(d);
1660 
1661     if (error)
1662         return error;
1663 
1664     REG_WRITE(&priv->regs->timecode, 0);
1665 
1666     return ROUTER_ERR_OK;
1667 }
1668 
1669 int router_tc_reset(void *d)
1670 {
1671     struct router_priv *priv = d;
1672     unsigned int tc;
1673     int error = router_check_open(d);
1674 
1675     if (error)
1676         return error;
1677 
1678     tc = REG_READ(&priv->regs->timecode);
1679     REG_WRITE(&priv->regs->timecode, tc | TC_RE);
1680 
1681     return ROUTER_ERR_OK;
1682 }
1683 
1684 int router_tc_get(void *d)
1685 {
1686     struct router_priv *priv = d;
1687     int error = router_check_open(d);
1688 
1689     if (error)
1690         return error;
1691 
1692     return (REG_READ(&priv->regs->timecode) & (TC_CF | TC_TC)) >> TC_TC_BIT;
1693 }
1694 
1695 int router_interrupt_unmask(void *d, int options)
1696 {
1697     struct router_priv *priv = d;
1698     unsigned int mask;
1699     int error = router_check_open(d);
1700 
1701     if (error)
1702         return error;
1703 
1704     #ifdef THREAD_SAFE
1705     /* Take device lock - Wait until we get semaphore */
1706     if (rtems_semaphore_obtain(priv->sem, RTEMS_WAIT, RTEMS_NO_TIMEOUT)
1707             != RTEMS_SUCCESSFUL) {
1708         DBG("ROUTER Sempahore failed\n");
1709         return ROUTER_ERR_ERROR;
1710     }
1711     #endif
1712 
1713     /* Unmask interrupts in ROTUER */
1714     /* Get previous mask */
1715     mask = REG_READ(&priv->regs->imask);
1716 
1717     /* Clear previous interrupts*/
1718     REG_WRITE(&priv->regs->pip, 0xffffffff);
1719 
1720     /* Set new mask */
1721     REG_WRITE(&priv->regs->imask, mask | options);
1722 
1723     #ifdef THREAD_SAFE
1724     /* Unlock dev */
1725     rtems_semaphore_release(priv->sem);
1726     #endif
1727 
1728     return ROUTER_ERR_OK;
1729 }
1730 
1731 int router_interrupt_mask(void *d, int options)
1732 {
1733     struct router_priv *priv = d;
1734     unsigned int mask;
1735     int error = router_check_open(d);
1736 
1737     if (error)
1738         return error;
1739 
1740     #ifdef THREAD_SAFE
1741     /* Take device lock - Wait until we get semaphore */
1742     if (rtems_semaphore_obtain(priv->sem, RTEMS_WAIT, RTEMS_NO_TIMEOUT)
1743             != RTEMS_SUCCESSFUL) {
1744         DBG("ROUTER Sempahore failed\n");
1745         return ROUTER_ERR_ERROR;
1746     }
1747     #endif
1748 
1749     /* Mask interrupts in ROTUER */
1750     /* Get previous mask */
1751     mask = REG_READ(&priv->regs->imask);
1752 
1753     /* Clear previous interrupts*/
1754     REG_WRITE(&priv->regs->pip, 0xffffffff);
1755 
1756     /* Set new mask */
1757     REG_WRITE(&priv->regs->imask, mask & ~(options));
1758 
1759     #ifdef THREAD_SAFE
1760     /* Unlock dev */
1761     rtems_semaphore_release(priv->sem);
1762     #endif
1763 
1764     return ROUTER_ERR_OK;
1765 }
1766 
1767 int router_port_interrupt_unmask(void *d, int port)
1768 {
1769     struct router_priv *priv = d;
1770     unsigned int mask;
1771     int error = router_check_port(d, port);
1772 
1773     if (error)
1774         return error;
1775 
1776     #ifdef THREAD_SAFE
1777     /* Take device lock - Wait until we get semaphore */
1778     if (rtems_semaphore_obtain(priv->sem, RTEMS_WAIT, RTEMS_NO_TIMEOUT)
1779             != RTEMS_SUCCESSFUL) {
1780         DBG("ROUTER Sempahore failed\n");
1781         return ROUTER_ERR_ERROR;
1782     }
1783     #endif
1784 
1785     /* Unmask interrupts in ROTUER */
1786     /* Get previous mask */
1787     mask = REG_READ(&priv->regs->ipmask);
1788 
1789     /* Clear previous interrupts*/
1790     REG_WRITE(&priv->regs->pip, (0x1 << port));
1791 
1792     /* Set new mask */
1793     REG_WRITE(&priv->regs->ipmask, mask | (0x1 << port));
1794 
1795     #ifdef THREAD_SAFE
1796     /* Unlock dev */
1797     rtems_semaphore_release(priv->sem);
1798     #endif
1799 
1800     return ROUTER_ERR_OK;
1801 }
1802 
1803 int router_port_interrupt_mask(void *d, int port)
1804 {
1805     struct router_priv *priv = d;
1806     unsigned int mask;
1807     int error = router_check_port(d, port);
1808 
1809     if (error)
1810         return error;
1811 
1812     #ifdef THREAD_SAFE
1813     /* Take device lock - Wait until we get semaphore */
1814     if (rtems_semaphore_obtain(priv->sem, RTEMS_WAIT, RTEMS_NO_TIMEOUT)
1815             != RTEMS_SUCCESSFUL) {
1816         DBG("ROUTER Sempahore failed\n");
1817         return ROUTER_ERR_ERROR;
1818     }
1819     #endif
1820 
1821     /* Mask interrupts in ROTUER */
1822     /* Get previous mask */
1823     mask = REG_READ(&priv->regs->ipmask);
1824 
1825     /* Clear previous interrupts*/
1826     REG_WRITE(&priv->regs->pip, (0x1 << port));
1827 
1828     /* Set new mask */
1829     REG_WRITE(&priv->regs->ipmask, mask & ~(0x1 << port));
1830 
1831     #ifdef THREAD_SAFE
1832     /* Unlock dev */
1833     rtems_semaphore_release(priv->sem);
1834     #endif
1835 
1836     return ROUTER_ERR_OK;
1837 }
1838 
1839 int router_reset(void *d)
1840 {
1841     struct router_priv *priv = d;
1842     int error = router_check_open(d);
1843 
1844     if (error)
1845         return error;
1846 
1847     /* Reset router */
1848     REG_WRITE(&priv->regs->cfgsts, RTRCFG_RE);
1849 
1850     return ROUTER_ERR_OK;
1851 }
1852 
1853 int router_icodegen_enable(void *d, uint8_t intn, uint32_t aitimer,
1854         int options)
1855 {
1856     struct router_priv *priv = d;
1857     int error = router_check_distint_support(d);
1858 
1859     if (error)
1860         return error;
1861 
1862     #ifdef THREAD_SAFE
1863     /* Take device lock - Wait until we get semaphore */
1864     if (rtems_semaphore_obtain(priv->sem, RTEMS_WAIT, RTEMS_NO_TIMEOUT)
1865             != RTEMS_SUCCESSFUL) {
1866         DBG("ROUTER Sempahore failed\n");
1867         return ROUTER_ERR_ERROR;
1868     }
1869     #endif
1870 
1871     REG_WRITE(&priv->regs->icodegen, (options & ~(ICODEGEN_IN)) |
1872             ICODEGEN_EN | (intn & ICODEGEN_IN));
1873 
1874     if (options & ICODEGEN_TE) {
1875         REG_WRITE(&priv->regs->aitimer, (aitimer & AITIMER_RL));
1876     }
1877 
1878     #ifdef THREAD_SAFE
1879     /* Unlock dev */
1880     rtems_semaphore_release(priv->sem);
1881     #endif
1882 
1883     return ROUTER_ERR_OK;
1884 }
1885 
1886 int router_icodegen_disable(void *d)
1887 {
1888     struct router_priv *priv = d;
1889     int error = router_check_distint_support(d);
1890 
1891     if (error)
1892         return error;
1893 
1894     REG_WRITE(&priv->regs->icodegen, ICODEGEN_TE);
1895 
1896     return ROUTER_ERR_OK;
1897 }
1898 
1899 int router_isrctimer_set(void *d, uint32_t reloadvalue)
1900 {
1901     struct router_priv *priv = d;
1902     int error = router_check_distint_support(d);
1903 
1904     if (error)
1905         return error;
1906 
1907     /* Set ISRC TIMER */
1908     REG_WRITE(&priv->regs->isrctimer, (reloadvalue & (ISRCTIMER_RL)));
1909 
1910     return ROUTER_ERR_OK;
1911 }
1912 
1913 int router_isrtimer_set(void *d, uint32_t reloadvalue)
1914 {
1915     struct router_priv *priv = d;
1916     int error = router_check_distint_support(d);
1917 
1918     if (error)
1919         return error;
1920 
1921     /* Set ISR TIMER */
1922     REG_WRITE(&priv->regs->isrtimer, (reloadvalue & (ISRTIMER_RL)));
1923 
1924     return ROUTER_ERR_OK;
1925 }
1926 
1927 int router_isrctimer_get(void *d, uint32_t *reloadvalue)
1928 {
1929     struct router_priv *priv = d;
1930     int error = router_check_distint_support(d);
1931 
1932     if (error)
1933         return error;
1934 
1935     if (reloadvalue == NULL) {
1936         DBG("ROUTER Wrong reloadvalue pointer\n");
1937         return ROUTER_ERR_EINVAL;
1938     }
1939 
1940     /* Set ISRC TIMER */
1941     *reloadvalue = REG_READ(&priv->regs->isrctimer) & (ISRCTIMER_RL);
1942 
1943     return ROUTER_ERR_OK;
1944 }
1945 
1946 int router_isrtimer_get(void *d, uint32_t *reloadvalue)
1947 {
1948     struct router_priv *priv = d;
1949     int error = router_check_distint_support(d);
1950 
1951     if (error)
1952         return error;
1953 
1954     if (reloadvalue == NULL) {
1955         DBG("ROUTER Wrong reloadvalue pointer\n");
1956         return ROUTER_ERR_EINVAL;
1957     }
1958 
1959     /* Set ISR TIMER */
1960     *reloadvalue = REG_READ(&priv->regs->isrtimer) & (ISRTIMER_RL);
1961 
1962     return ROUTER_ERR_OK;
1963 }
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