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0001 /* SPDX-License-Identifier: BSD-2-Clause */
0002 
0003 /*  GRLIB GRPCI2 PCI HOST driver.
0004  * 
0005  *  COPYRIGHT (c) 2011
0006  *  Cobham Gaisler AB.
0007  *
0008  * Redistribution and use in source and binary forms, with or without
0009  * modification, are permitted provided that the following conditions
0010  * are met:
0011  * 1. Redistributions of source code must retain the above copyright
0012  *    notice, this list of conditions and the following disclaimer.
0013  * 2. Redistributions in binary form must reproduce the above copyright
0014  *    notice, this list of conditions and the following disclaimer in the
0015  *    documentation and/or other materials provided with the distribution.
0016  *
0017  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
0018  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
0019  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
0020  * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
0021  * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
0022  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
0023  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
0024  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
0025  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
0026  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
0027  * POSSIBILITY OF SUCH DAMAGE.
0028  */
0029 
0030 /* Configures the GRPCI2 core and initialize,
0031  *  - the PCI Library (pci.c)
0032  *  - the general part of the PCI Bus driver (pci_bus.c)
0033  *  
0034  * System interrupt assigned to PCI interrupt (INTA#..INTD#) is by
0035  * default taken from Plug and Play, but may be overridden by the 
0036  * driver resources INTA#..INTD#. GRPCI2 handles differently depending
0037  * on the design (4 different ways).
0038  *
0039  * GRPCI2 IRQ implementation notes
0040  * -------------------------------
0041  * Since the Driver Manager pci_bus layer implements IRQ by calling
0042  * pci_interrupt_* which translates into BSP_shared_interrupt_*, and the
0043  * root-bus also relies on BSP_shared_interrupt_*, it is safe for the GRPCI2
0044  * driver to use the drvmgr_interrupt_* routines since they will be
0045  * accessing the same routines in the end. Otherwise the GRPCI2 driver must
0046  * have used the pci_interrupt_* routines.
0047  */
0048 
0049 #include <stdlib.h>
0050 #include <stdio.h>
0051 #include <string.h>
0052 #include <rtems.h>
0053 #include <rtems/bspIo.h>
0054 #include <libcpu/byteorder.h>
0055 #include <libcpu/access.h>
0056 #include <pci.h>
0057 #include <pci/cfg.h>
0058 
0059 #include <drvmgr/drvmgr.h>
0060 #include <grlib/ambapp_bus.h>
0061 #include <grlib/ambapp.h>
0062 #include <drvmgr/pci_bus.h>
0063 #include <grlib/grpci2.h>
0064 
0065 #include <grlib/grlib_impl.h>
0066 
0067 /* If defined to 1 - byte twisting is enabled by default */
0068 #define DEFAULT_BT_ENABLED 0
0069 
0070 /* If defined to 64 - Latency timer is 64 by default */
0071 #define DEFAULT_LATENCY_TIMER 64
0072 
0073 /* Interrupt assignment. Set to other value than 0xff in order to 
0074  * override defaults and plug&play information
0075  */
0076 #ifndef GRPCI2_INTA_SYSIRQ
0077  #define GRPCI2_INTA_SYSIRQ 0xff
0078 #endif
0079 #ifndef GRPCI2_INTB_SYSIRQ
0080  #define GRPCI2_INTB_SYSIRQ 0xff
0081 #endif
0082 #ifndef GRPCI2_INTC_SYSIRQ
0083  #define GRPCI2_INTC_SYSIRQ 0xff
0084 #endif
0085 #ifndef GRPCI2_INTD_SYSIRQ
0086  #define GRPCI2_INTD_SYSIRQ 0xff
0087 #endif
0088 
0089 /*#define DEBUG 1*/
0090 
0091 #ifdef DEBUG
0092 #define DBG(x...) printk(x)
0093 #else
0094 #define DBG(x...) 
0095 #endif
0096 
0097 /*
0098  * GRPCI2 APB Register MAP
0099  */
0100 struct grpci2_regs {
0101     volatile unsigned int ctrl;     /* 0x00 */
0102     volatile unsigned int sts_cap;      /* 0x04 */
0103     volatile unsigned int ppref;        /* 0x08 */
0104     volatile unsigned int io_map;       /* 0x0C */
0105     volatile unsigned int dma_ctrl;     /* 0x10 */
0106     volatile unsigned int dma_bdbase;   /* 0x14 */
0107     volatile unsigned int dma_chact;    /* 0x18 */
0108     int res1;               /* 0x1C */
0109     volatile unsigned int bars[6];      /* 0x20 */
0110     int res2[2];                /* 0x38 */
0111     volatile unsigned int ahbmst_map[16];   /* 0x40 */
0112 };
0113 
0114 #define CTRL_BUS_BIT 16
0115 
0116 #define CTRL_SI (1<<27)
0117 #define CTRL_PE (1<<26)
0118 #define CTRL_ER (1<<25)
0119 #define CTRL_EI (1<<24)
0120 #define CTRL_BUS (0xff<<CTRL_BUS_BIT)
0121 #define CTRL_HOSTINT 0xf
0122 
0123 #define STS_HOST_BIT    31
0124 #define STS_MST_BIT 30
0125 #define STS_TAR_BIT 29
0126 #define STS_DMA_BIT 28
0127 #define STS_DI_BIT  27
0128 #define STS_HI_BIT  26
0129 #define STS_IRQMODE_BIT 24
0130 #define STS_TRACE_BIT   23
0131 #define STS_CFGERRVALID_BIT 20
0132 #define STS_CFGERR_BIT  19
0133 #define STS_INTTYPE_BIT 12
0134 #define STS_INTSTS_BIT  8
0135 #define STS_FDEPTH_BIT  2
0136 #define STS_FNUM_BIT    0
0137 
0138 #define STS_HOST    (1<<STS_HOST_BIT)
0139 #define STS_MST     (1<<STS_MST_BIT)
0140 #define STS_TAR     (1<<STS_TAR_BIT)
0141 #define STS_DMA     (1<<STS_DMA_BIT)
0142 #define STS_DI      (1<<STS_DI_BIT)
0143 #define STS_HI      (1<<STS_HI_BIT)
0144 #define STS_IRQMODE (0x3<<STS_IRQMODE_BIT)
0145 #define STS_TRACE   (1<<STS_TRACE_BIT)
0146 #define STS_CFGERRVALID (1<<STS_CFGERRVALID_BIT)
0147 #define STS_CFGERR  (1<<STS_CFGERR_BIT)
0148 #define STS_INTTYPE (0x7f<<STS_INTTYPE_BIT)
0149 #define STS_INTSTS  (0xf<<STS_INTSTS_BIT)
0150 #define STS_FDEPTH  (0x7<<STS_FDEPTH_BIT)
0151 #define STS_FNUM    (0x3<<STS_FNUM_BIT)
0152 
0153 #define STS_ITIMEOUT    (1<<18)
0154 #define STS_ISYSERR (1<<17)
0155 #define STS_IDMA    (1<<16)
0156 #define STS_IDMAERR (1<<15)
0157 #define STS_IMSTABRT    (1<<14)
0158 #define STS_ITGTABRT    (1<<13)
0159 #define STS_IPARERR (1<<12)
0160 
0161 /* GRPCI2 Capability */
0162 struct grpci2_cap_first {
0163     unsigned int ctrl;
0164     unsigned int pci2ahb_map[6];
0165     unsigned int ext2ahb_map;
0166     unsigned int io_map;
0167     unsigned int pcibar_size[6];
0168     unsigned int ahb_pref;
0169 };
0170 #define CAP9_CTRL_OFS 0
0171 #define CAP9_BAR_OFS 0x4
0172 #define CAP9_IOMAP_OFS 0x20
0173 #define CAP9_BARSIZE_OFS 0x24
0174 #define CAP9_AHBPREF_OFS 0x3C
0175 
0176 /* Used internally for accessing the PCI bridge's configuration space itself */
0177 #define HOST_TGT PCI_DEV(0xff, 0, 0)
0178 
0179 struct grpci2_priv *grpci2priv = NULL;
0180 
0181 /* PCI Interrupt assignment. Connects an PCI interrupt pin (INTA#..INTD#)
0182  * to a system interrupt number.
0183  */
0184 unsigned char grpci2_pci_irq_table[4] =
0185 {
0186     /* INTA# */ GRPCI2_INTA_SYSIRQ,
0187     /* INTB# */ GRPCI2_INTB_SYSIRQ,
0188     /* INTC# */ GRPCI2_INTC_SYSIRQ,
0189     /* INTD# */ GRPCI2_INTD_SYSIRQ
0190 };
0191 
0192 /* Start of workspace/dynamical area */
0193 extern unsigned int _end;
0194 #define DMA_START ((unsigned int) &_end)
0195 
0196 /* Default BAR mapping, set BAR0 256MB 1:1 mapped base of CPU RAM */
0197 struct grpci2_pcibar_cfg grpci2_default_bar_mapping[6] = {
0198     /* BAR0 */ {DMA_START, DMA_START, 0x10000000},
0199     /* BAR1 */ {0, 0, 0},
0200     /* BAR2 */ {0, 0, 0},
0201     /* BAR3 */ {0, 0, 0},
0202     /* BAR4 */ {0, 0, 0},
0203     /* BAR5 */ {0, 0, 0},
0204 };
0205 
0206 /* Driver private data struture */
0207 struct grpci2_priv {
0208     struct drvmgr_dev       *dev;
0209     struct grpci2_regs      *regs;
0210     unsigned char           ver;
0211     char                irq;
0212     char                irq_mode; /* IRQ Mode from CAPSTS REG */
0213     char                irq_dma; /* IRQ Index for DMA */
0214     char                bt_enabled;
0215     unsigned int            irq_mask;
0216     unsigned int            latency_timer;
0217 
0218     struct grpci2_pcibar_cfg    *barcfg;
0219 
0220     unsigned int            pci_area;
0221     unsigned int            pci_area_end;
0222     unsigned int            pci_io;    
0223     unsigned int            pci_conf;
0224     unsigned int            pci_conf_end;
0225 
0226     uint32_t            devVend; /* Host PCI Device/Vendor ID */
0227 
0228     struct drvmgr_map_entry     maps_up[7];
0229     struct drvmgr_map_entry     maps_down[2];
0230     struct pcibus_config        config;
0231 
0232     /* DMA interrupts */
0233     void (*dma_isr)(void *data);
0234     void *dma_isr_arg;
0235 
0236     SPIN_DECLARE(devlock)
0237 };
0238 
0239 int grpci2_init1(struct drvmgr_dev *dev);
0240 int grpci2_init3(struct drvmgr_dev *dev);
0241 void grpci2_err_isr(void *arg);
0242 void grpci2_dma_isr(void *arg);
0243 
0244 /* GRPCI2 DRIVER */
0245 
0246 struct drvmgr_drv_ops grpci2_ops = 
0247 {
0248     .init = {grpci2_init1, NULL, grpci2_init3, NULL},
0249     .remove = NULL,
0250     .info = NULL
0251 };
0252 
0253 struct amba_dev_id grpci2_ids[] = 
0254 {
0255     {VENDOR_GAISLER, GAISLER_GRPCI2},
0256     {0, 0}      /* Mark end of table */
0257 };
0258 
0259 struct amba_drv_info grpci2_info =
0260 {
0261     {
0262         DRVMGR_OBJ_DRV,                 /* Driver */
0263         NULL,               /* Next driver */
0264         NULL,               /* Device list */
0265         DRIVER_AMBAPP_GAISLER_GRPCI2_ID,/* Driver ID */
0266         "GRPCI2_DRV",           /* Driver Name */
0267         DRVMGR_BUS_TYPE_AMBAPP,     /* Bus Type */
0268         &grpci2_ops,
0269         NULL,               /* Funcs */
0270         0,              /* No devices yet */
0271         sizeof(struct grpci2_priv), /* Make drvmgr alloc private */
0272     },
0273     &grpci2_ids[0]
0274 };
0275 
0276 /* Defaults to do nothing - user can override this function
0277  * by including the DMA DRIVER.
0278  */
0279 int __attribute__((weak)) grpci2dma_init(void * regs, void isr_register( void (*isr)(void *), void * arg));
0280 
0281 int grpci2dma_init(void * regs, void isr_register( void (*isr)(void *), void * arg))
0282 {
0283     return 0;
0284 }
0285 
0286 /* Prototype of grpci2_dma_isr_register function */
0287 static void grpci2_dma_isr_register( void (*isr)(void *), void * arg);
0288 
0289 void grpci2_register_drv(void)
0290 {
0291     DBG("Registering GRPCI2 driver\n");
0292     drvmgr_drv_register(&grpci2_info.general);
0293 }
0294 
0295 static int grpci2_cfg_r32(pci_dev_t dev, int ofs, uint32_t *val)
0296 {
0297     struct grpci2_priv *priv = grpci2priv;
0298     volatile uint32_t *pci_conf;
0299     unsigned int tmp, devfn;
0300     int retval, bus = PCI_DEV_BUS(dev);
0301     SPIN_IRQFLAGS(irqflags);
0302 
0303     if ((unsigned int)ofs & 0xffffff03) {
0304         retval = PCISTS_EINVAL;
0305         goto out2;
0306     }
0307 
0308     if (PCI_DEV_SLOT(dev) > 15) {
0309         retval = PCISTS_MSTABRT;
0310         goto out;
0311     }
0312 
0313     /* GRPCI2 can access "non-standard" devices on bus0 (on AD11.AD16), 
0314      * we skip them.
0315      */
0316     if (dev == HOST_TGT)
0317         bus = devfn = 0;
0318     else if (bus == 0)
0319         devfn = PCI_DEV_DEVFUNC(dev) + PCI_DEV(0, 6, 0);
0320     else
0321         devfn = PCI_DEV_DEVFUNC(dev);
0322 
0323     pci_conf = (volatile uint32_t *) (priv->pci_conf | (devfn << 8) | ofs);
0324 
0325     SPIN_LOCK_IRQ(&priv->devlock, irqflags);
0326 
0327     /* Select bus */
0328     priv->regs->ctrl = (priv->regs->ctrl & ~(0xff<<16)) | (bus<<16);
0329     /* clear old status */
0330     priv->regs->sts_cap = (STS_CFGERR | STS_CFGERRVALID);
0331 
0332     tmp = *pci_conf;
0333 
0334     /* Wait until GRPCI2 signals that CFG access is done, it should be
0335      * done instantaneously unless a DMA operation is ongoing...
0336      */
0337     while ((priv->regs->sts_cap & STS_CFGERRVALID) == 0)
0338         ;
0339 
0340     if (priv->regs->sts_cap & STS_CFGERR) {
0341         retval = PCISTS_MSTABRT;
0342     } else {
0343         /* Bus always little endian (unaffected by byte-swapping) */
0344         *val = CPU_swap_u32(tmp);
0345         retval = PCISTS_OK;
0346     }
0347 
0348     SPIN_UNLOCK_IRQ(&priv->devlock, irqflags);
0349 
0350 out:
0351     if (retval != PCISTS_OK)
0352         *val = 0xffffffff;
0353 
0354     DBG("pci_read: [%x:%x:%x] reg: 0x%x => addr: 0x%x, val: 0x%x  (%d)\n",
0355         PCI_DEV_EXPAND(dev), ofs, pci_conf, *val, retval);
0356 
0357 out2:
0358     return retval;
0359 }
0360 
0361 static int grpci2_cfg_r16(pci_dev_t dev, int ofs, uint16_t *val)
0362 {
0363     uint32_t v;
0364     int retval;
0365 
0366     if (ofs & 1)
0367         return PCISTS_EINVAL;
0368 
0369     retval = grpci2_cfg_r32(dev, ofs & ~0x3, &v);
0370     *val = 0xffff & (v >> (8*(ofs & 0x3)));
0371 
0372     return retval;
0373 }
0374 
0375 static int grpci2_cfg_r8(pci_dev_t dev, int ofs, uint8_t *val)
0376 {
0377     uint32_t v;
0378     int retval;
0379 
0380     retval = grpci2_cfg_r32(dev, ofs & ~0x3, &v);
0381 
0382     *val = 0xff & (v >> (8*(ofs & 3)));
0383 
0384     return retval;
0385 }
0386 
0387 static int grpci2_cfg_w32(pci_dev_t dev, int ofs, uint32_t val)
0388 {
0389     struct grpci2_priv *priv = grpci2priv;
0390     volatile uint32_t *pci_conf;
0391     uint32_t value, devfn;
0392     int retval, bus = PCI_DEV_BUS(dev);
0393     SPIN_IRQFLAGS(irqflags);
0394 
0395     if ((unsigned int)ofs & 0xffffff03)
0396         return PCISTS_EINVAL;
0397 
0398     if (PCI_DEV_SLOT(dev) > 15)
0399         return PCISTS_MSTABRT;
0400 
0401     value = CPU_swap_u32(val);
0402 
0403     /* GRPCI2 can access "non-standard" devices on bus0 (on AD11.AD16), 
0404      * we skip them.
0405      */
0406     if (dev == HOST_TGT)
0407         bus = devfn = 0;
0408     else if (bus == 0)
0409         devfn = PCI_DEV_DEVFUNC(dev) + PCI_DEV(0, 6, 0);
0410     else
0411         devfn = PCI_DEV_DEVFUNC(dev);
0412 
0413     pci_conf = (volatile uint32_t *) (priv->pci_conf | (devfn << 8) | ofs);
0414 
0415     SPIN_LOCK_IRQ(&priv->devlock, irqflags);
0416 
0417     /* Select bus */
0418     priv->regs->ctrl = (priv->regs->ctrl & ~(0xff<<16)) | (bus<<16);
0419     /* clear old status */
0420     priv->regs->sts_cap = (STS_CFGERR | STS_CFGERRVALID);
0421 
0422     *pci_conf = value;
0423 
0424     /* Wait until GRPCI2 signals that CFG access is done, it should be
0425      * done instantaneously unless a DMA operation is ongoing...
0426      */
0427     while ((priv->regs->sts_cap & STS_CFGERRVALID) == 0)
0428         ;
0429 
0430     if (priv->regs->sts_cap & STS_CFGERR)
0431         retval = PCISTS_MSTABRT;
0432     else
0433         retval = PCISTS_OK;
0434 
0435     SPIN_UNLOCK_IRQ(&priv->devlock, irqflags);
0436 
0437     DBG("pci_write - [%x:%x:%x] reg: 0x%x => addr: 0x%x, val: 0x%x  (%d)\n",
0438         PCI_DEV_EXPAND(dev), ofs, pci_conf, value, retval);
0439 
0440     return retval;
0441 }
0442 
0443 static int grpci2_cfg_w16(pci_dev_t dev, int ofs, uint16_t val)
0444 {
0445     uint32_t v;
0446     int retval;
0447 
0448     if (ofs & 1)
0449         return PCISTS_EINVAL;
0450 
0451     retval = grpci2_cfg_r32(dev, ofs & ~0x3, &v);
0452     if (retval != PCISTS_OK)
0453         return retval;
0454 
0455     v = (v & ~(0xffff << (8*(ofs&3)))) | ((0xffff&val) << (8*(ofs&3)));
0456 
0457     return grpci2_cfg_w32(dev, ofs & ~0x3, v);
0458 }
0459 
0460 static int grpci2_cfg_w8(pci_dev_t dev, int ofs, uint8_t val)
0461 {
0462     uint32_t v;
0463     int retval;
0464 
0465     retval = grpci2_cfg_r32(dev, ofs & ~0x3, &v);
0466     if (retval != PCISTS_OK)
0467         return retval;
0468 
0469     v = (v & ~(0xff << (8*(ofs&3)))) | ((0xff&val) << (8*(ofs&3)));
0470 
0471     return grpci2_cfg_w32(dev, ofs & ~0x3, v);
0472 }
0473 
0474 /* Return the assigned system IRQ number that corresponds to the PCI
0475  * "Interrupt Pin" information from configuration space.
0476  *
0477  * The IRQ information is stored in the grpci2_pci_irq_table configurable
0478  * by the user.
0479  *
0480  * Returns the "system IRQ" for the PCI INTA#..INTD# pin in irq_pin. Returns
0481  * 0xff if not assigned.
0482  */
0483 static uint8_t grpci2_bus0_irq_map(pci_dev_t dev, int irq_pin)
0484 {
0485     uint8_t sysIrqNr = 0; /* not assigned */
0486     int irq_group;
0487 
0488     if ( (irq_pin >= 1) && (irq_pin <= 4) ) {
0489         /* Use default IRQ decoding on PCI BUS0 according slot numbering */
0490         irq_group = PCI_DEV_SLOT(dev) & 0x3;
0491         irq_pin = ((irq_pin - 1) + irq_group) & 0x3;
0492         /* Valid PCI "Interrupt Pin" number */
0493         sysIrqNr = grpci2_pci_irq_table[irq_pin];
0494     }
0495     return sysIrqNr;
0496 }
0497 
0498 static int grpci2_translate(uint32_t *address, int type, int dir)
0499 {
0500     uint32_t adr, start, end;
0501     struct grpci2_priv *priv = grpci2priv;
0502     int i;
0503 
0504     if (type == 1) {
0505         /* I/O */
0506         if (dir != 0) {
0507             /* The PCI bus can not access the CPU bus from I/O
0508              * because GRPCI2 core does not support I/O BARs
0509              */
0510             return -1;
0511         }
0512 
0513         /* We have got a PCI IO BAR address that the CPU want to access.
0514          * Check that it is within the PCI I/O window, I/O adresses
0515          * are NOT mapped 1:1 with GRPCI2 driver... translation needed.
0516          */
0517         adr = *(uint32_t *)address;
0518         if (adr < 0x100 || adr > 0x10000)
0519             return -1;
0520         *address = adr + priv->pci_io;
0521     } else {
0522         /* MEMIO and MEM.
0523          * Memory space is mapped 1:1 so no translation is needed.
0524          * Check that address is within accessible windows.
0525          */
0526         adr = *(uint32_t *)address;
0527         if (dir == 0) {
0528             /* PCI BAR to AMBA-CPU address.. check that it is
0529              * located within GRPCI2 PCI Memory Window
0530              * adr = PCI address.
0531              */
0532             if (adr < priv->pci_area || adr >= priv->pci_area_end)
0533                 return -1;
0534         } else {
0535             /* We have a CPU address and want to get access to it
0536              * from PCI space, typically when doing DMA into CPU
0537              * RAM. The GRPCI2 core may have multiple target BARs
0538              * that PCI masters can access, the BARs are user
0539              * configurable in the following ways:
0540              *  BAR_SIZE, PCI_BAR Address and MAPPING (AMBA ADR)
0541              *
0542              * The below code tries to find a BAR for which the
0543              * AMBA bar may have been mapped onto, and translate
0544              * the AMBA-CPU address into a PCI address using the
0545              * given mapping.
0546              *
0547              * adr = AMBA address.
0548              */
0549             for(i=0; i<6; i++) {
0550                 start = priv->barcfg[i].ahbadr;
0551                 end = priv->barcfg[i].ahbadr +
0552                     priv->barcfg[i].barsize;
0553                 if (adr >= start && adr < end) {
0554                     /* BAR match: Translate address */
0555                     *address = (adr - start) +
0556                         priv->barcfg[i].pciadr;
0557                     return 0;
0558                 }
0559             }
0560             return -1;
0561         }
0562     }
0563 
0564     return 0;
0565 }
0566 
0567 extern struct pci_memreg_ops pci_memreg_sparc_le_ops;
0568 extern struct pci_memreg_ops pci_memreg_sparc_be_ops;
0569 
0570 /* GRPCI2 PCI access routines, default to Little-endian PCI Bus */
0571 struct pci_access_drv grpci2_access_drv = {
0572     .cfg =
0573     {
0574         grpci2_cfg_r8,
0575         grpci2_cfg_r16,
0576         grpci2_cfg_r32,
0577         grpci2_cfg_w8,
0578         grpci2_cfg_w16,
0579         grpci2_cfg_w32,
0580     },
0581     .io =
0582     {
0583         _ld8,
0584         _ld_le16,
0585         _ld_le32,
0586         _st8,
0587         _st_le16,
0588         _st_le32,
0589     },
0590     .memreg = &pci_memreg_sparc_le_ops,
0591     .translate = grpci2_translate,
0592 };
0593 
0594 struct pci_io_ops grpci2_io_ops_be =
0595 {
0596     _ld8,
0597     _ld_be16,
0598     _ld_be32,
0599     _st8,
0600     _st_be16,
0601     _st_be32,
0602 };
0603 
0604 /* PCI Error Interrupt handler, called when there may be a PCI Target/Master
0605  * Abort.
0606  */
0607 void grpci2_err_isr(void *arg)
0608 {
0609     struct grpci2_priv *priv = arg;
0610     unsigned int sts = priv->regs->sts_cap;
0611 
0612     if (sts & (STS_IMSTABRT | STS_ITGTABRT | STS_IPARERR | STS_ISYSERR | STS_ITIMEOUT)) {
0613         /* A PCI error IRQ ... Error handler unimplemented
0614          * add your code here...
0615          */
0616         if (sts & STS_IMSTABRT) {
0617             printk("GRPCI2: unhandled Master Abort IRQ\n");
0618         }
0619         if (sts & STS_ITGTABRT) {
0620             printk("GRPCI2: unhandled Target Abort IRQ\n");
0621         }
0622         if (sts & STS_IPARERR) {
0623             printk("GRPCI2: unhandled Parity Error IRQ\n");
0624         }
0625         if (sts & STS_ISYSERR) {
0626             printk("GRPCI2: unhandled System Error IRQ\n");
0627         }
0628         if (sts & STS_ITIMEOUT) {
0629             printk("GRPCI2: unhandled PCI target access timeout IRQ\n");
0630         }
0631     }
0632 }
0633 
0634 /* PCI DMA Interrupt handler, called when there may be a PCI DMA interrupt.
0635  */
0636 void grpci2_dma_isr(void *arg)
0637 {
0638     struct grpci2_priv *priv = arg;
0639     unsigned int sts = (priv->regs->sts_cap & (STS_IDMAERR | STS_IDMA));
0640 
0641     /* Clear Interrupt if taken*/
0642     if (sts != 0){
0643         /* Clear IDMAERR and IDMA bits */
0644         priv->regs->sts_cap = (STS_IDMAERR | STS_IDMA);
0645         /* Clear DRVMGR interrupt */
0646         drvmgr_interrupt_clear(priv->dev, priv->irq_dma);
0647         /* Call DMA driver ISR */
0648         (priv->dma_isr)(priv->dma_isr_arg);
0649     }
0650 }
0651 
0652 static int grpci2_hw_init(struct grpci2_priv *priv)
0653 {
0654     struct grpci2_regs *regs = priv->regs;
0655     int i;
0656     uint8_t capptr;
0657     uint32_t data, io_map, ahbadr, pciadr, size;
0658     pci_dev_t host = HOST_TGT;
0659     struct grpci2_pcibar_cfg *barcfg = priv->barcfg;
0660 
0661     /* Reset any earlier setup */
0662     regs->ctrl = 0;
0663     regs->sts_cap = ~0; /* Clear Status */
0664     regs->dma_ctrl = 0;
0665     regs->dma_bdbase = 0;
0666 
0667     /* Translate I/O accesses 1:1, (will not work for PCI 2.3) */
0668     regs->io_map = priv->pci_io & 0xffff0000;
0669 
0670     /* set 1:1 mapping between AHB -> PCI memory space, for all Masters
0671      * Each AHB master has it's own mapping registers. Max 16 AHB masters.
0672      */
0673     for (i=0; i<16; i++)
0674         regs->ahbmst_map[i] = priv->pci_area;
0675 
0676     /* Get the GRPCI2 Host PCI ID */
0677     grpci2_cfg_r32(host, PCIR_VENDOR, &priv->devVend);
0678 
0679     /* Get address to first (always defined) capability structure */
0680     grpci2_cfg_r8(host, PCIR_CAP_PTR, &capptr);
0681     if (capptr == 0)
0682         return -1;
0683 
0684     /* Limit the prefetch for GRPCI2 version 0. */
0685     if (priv->ver == 0)
0686         grpci2_cfg_w32(host, capptr+CAP9_AHBPREF_OFS, 0);
0687 
0688     /* Enable/Disable Byte twisting */
0689     grpci2_cfg_r32(host, capptr+CAP9_IOMAP_OFS, &io_map);
0690     io_map = (io_map & ~0x1) | (priv->bt_enabled ? 1 : 0);
0691     grpci2_cfg_w32(host, capptr+CAP9_IOMAP_OFS, io_map);
0692 
0693     /* Setup the Host's PCI Target BARs for others to access (DMA) */
0694     for (i=0; i<6; i++) {
0695         /* Make sure address is properly aligned */
0696         size = ~(barcfg[i].barsize-1);
0697         barcfg[i].pciadr &= size;
0698         barcfg[i].ahbadr &= size;
0699 
0700         pciadr = barcfg[i].pciadr;
0701         ahbadr = barcfg[i].ahbadr;
0702         size |= PCIM_BAR_MEM_PREFETCH;
0703 
0704         grpci2_cfg_w32(host, capptr+CAP9_BARSIZE_OFS+i*4, size);
0705         grpci2_cfg_w32(host, capptr+CAP9_BAR_OFS+i*4, ahbadr);
0706         grpci2_cfg_w32(host, PCIR_BAR(0)+i*4, pciadr);
0707     }
0708 
0709     /* set as bus master and enable pci memory responses */  
0710     grpci2_cfg_r32(host, PCIR_COMMAND, &data);
0711     data |= (PCIM_CMD_MEMEN | PCIM_CMD_BUSMASTEREN);
0712     grpci2_cfg_w32(host, PCIR_COMMAND, data);
0713 
0714     /* set latency timer */
0715     grpci2_cfg_r32(host, PCIR_CACHELNSZ, &data);
0716     data &= ~0xff00;
0717     data |= ((priv->latency_timer & 0xff) << 8);
0718     grpci2_cfg_w32(host, PCIR_CACHELNSZ, data);
0719 
0720     /* Enable Error respone (CPU-TRAP) on illegal memory access */
0721     regs->ctrl = CTRL_ER | CTRL_PE;
0722 
0723     /* Successful */
0724     return 0;
0725 }
0726 
0727 /* Initializes the GRPCI2 core and driver, must be called before calling
0728  * init_pci()
0729  *
0730  * Return values
0731  *  0             Successful initalization
0732  *  -1            Error during initialization, for example "PCI core not found".
0733  *  -2            Error PCI controller not HOST (targets not supported)
0734  *  -3            Error due to GRPCI2 hardware initialization
0735  */
0736 static int grpci2_init(struct grpci2_priv *priv)
0737 {
0738     struct ambapp_apb_info *apb;
0739     struct ambapp_ahb_info *ahb;
0740     int pin, i, j;
0741     union drvmgr_key_value *value;
0742     char keyname[6];
0743     struct amba_dev_info *ainfo = priv->dev->businfo;
0744     struct grpci2_pcibar_cfg *barcfg;
0745     unsigned int size;
0746 
0747     /* Find PCI core from Plug&Play information */
0748     apb = ainfo->info.apb_slv;
0749     ahb = ainfo->info.ahb_slv;
0750 
0751     /* Found PCI core, init private structure */
0752     priv->irq = apb->common.irq;
0753     priv->ver = apb->common.ver;
0754     priv->regs = (struct grpci2_regs *)apb->start;
0755     priv->bt_enabled = DEFAULT_BT_ENABLED;
0756     priv->irq_mode = (priv->regs->sts_cap & STS_IRQMODE) >> STS_IRQMODE_BIT;
0757     priv->latency_timer = DEFAULT_LATENCY_TIMER;
0758 
0759     /* Initialize Spin-lock for GRPCI2 Device. */
0760     SPIN_INIT(&priv->devlock, "grpci2");
0761 
0762     /* Calculate the PCI windows 
0763      *  AMBA->PCI Window:                       AHB SLAVE AREA0
0764      *  AMBA->PCI I/O cycles Window:            AHB SLAVE AREA1 Lower half
0765      *  AMBA->PCI Configuration cycles Window:  AHB SLAVE AREA1 Upper half
0766      */
0767     priv->pci_area     = ahb->start[0];
0768     priv->pci_area_end = ahb->start[0] + ahb->mask[0];
0769     priv->pci_io       = ahb->start[1];
0770     priv->pci_conf     = ahb->start[1] + 0x10000;
0771     priv->pci_conf_end = priv->pci_conf + 0x10000;
0772 
0773     /* On systems where PCI I/O area and configuration area is apart of the
0774      * "PCI Window" the PCI Window stops at the start of the PCI I/O area
0775      */
0776     if ((priv->pci_io > priv->pci_area) &&
0777         (priv->pci_io < (priv->pci_area_end-1))) {
0778         priv->pci_area_end = priv->pci_io;
0779     }
0780 
0781     /* Init PCI interrupt assignment table to all use the interrupt routed
0782      * through the GRPCI2 core.
0783      */
0784     strcpy(keyname, "INTX#");
0785     for (pin=1; pin<5; pin++) {
0786         if (grpci2_pci_irq_table[pin-1] == 0xff) {
0787             if (priv->irq_mode < 2) {
0788                 /* PCI Interrupts are shared */
0789                 grpci2_pci_irq_table[pin-1] = priv->irq;
0790             } else {
0791                 /* Unique IRQ per PCI INT Pin */
0792                 grpci2_pci_irq_table[pin-1] = priv->irq + pin-1;
0793             }
0794 
0795             /* User may override Both hardcoded IRQ setup and Plug & Play IRQ */
0796             keyname[3] = 'A' + (pin-1);
0797             value = drvmgr_dev_key_get(priv->dev, keyname, DRVMGR_KT_INT);
0798             if (value)
0799                 grpci2_pci_irq_table[pin-1] = value->i;
0800         }
0801 
0802         /* Remember which IRQs are enabled */
0803         if (grpci2_pci_irq_table[pin-1] != 0)
0804             priv->irq_mask |= 1 << (pin-1);
0805     }
0806 
0807     /* User may override DEFAULT_BT_ENABLED to enable/disable byte twisting */
0808     value = drvmgr_dev_key_get(priv->dev, "byteTwisting", DRVMGR_KT_INT);
0809     if (value)
0810         priv->bt_enabled = value->i;
0811 
0812     /* Let user Configure the 6 target BARs */
0813     value = drvmgr_dev_key_get(priv->dev, "tgtBarCfg", DRVMGR_KT_POINTER);
0814     if (value)
0815         priv->barcfg = value->ptr;
0816     else
0817         priv->barcfg = grpci2_default_bar_mapping;
0818 
0819     /* User may override DEFAULT_LATENCY_TIMER */
0820     value = drvmgr_dev_key_get(priv->dev, "latencyTimer", DRVMGR_KT_INT);
0821     if (value)
0822         priv->latency_timer = value->i;
0823 
0824     /* This driver only support HOST systems, we check that it can act as a 
0825      * PCI Master and that it is in the Host slot. */
0826     if ((priv->regs->sts_cap&STS_HOST) || !(priv->regs->sts_cap&STS_MST))
0827         return -2; /* Target not supported */
0828 
0829     /* Init the PCI Core */
0830     if (grpci2_hw_init(priv))
0831         return -3;
0832 
0833     /* Down streams translation table */
0834     priv->maps_down[0].name = "AMBA -> PCI MEM Window";
0835     priv->maps_down[0].size = priv->pci_area_end - priv->pci_area;
0836     priv->maps_down[0].from_adr = (void *)priv->pci_area;
0837     priv->maps_down[0].to_adr = (void *)priv->pci_area;
0838     /* End table */
0839     priv->maps_down[1].size = 0;
0840 
0841     /* Up streams translation table */
0842     /* Setup the Host's PCI Target BARs for others to access (DMA) */
0843     barcfg = priv->barcfg;
0844     for (i=0,j=0; i<6; i++) {
0845         size = barcfg[i].barsize;
0846         if (size == 0)
0847             continue;
0848 
0849         /* Make sure address is properly aligned */
0850         priv->maps_up[j].name = "Target BAR[I] -> AMBA";
0851         priv->maps_up[j].size = size;
0852         priv->maps_up[j].from_adr = (void *)
0853                     (barcfg[i].pciadr & ~(size - 1));
0854         priv->maps_up[j].to_adr = (void *)
0855                     (barcfg[i].ahbadr & ~(size - 1));
0856         j++;
0857     }
0858 
0859     /* End table */
0860     priv->maps_up[j].size = 0;
0861 
0862     return 0;
0863 }
0864 
0865 /* Called when a core is found with the AMBA device and vendor ID 
0866  * given in grpci2_ids[]. IRQ, Console does not work here
0867  */
0868 int grpci2_init1(struct drvmgr_dev *dev)
0869 {
0870     int status;
0871     struct grpci2_priv *priv;
0872     struct pci_auto_setup grpci2_auto_cfg;
0873 
0874     DBG("GRPCI2[%d] on bus %s\n", dev->minor_drv, dev->parent->dev->name);
0875 
0876     if (grpci2priv) {
0877         DBG("Driver only supports one PCI core\n");
0878         return DRVMGR_FAIL;
0879     }
0880 
0881     if ((strcmp(dev->parent->dev->drv->name, "AMBAPP_GRLIB_DRV") != 0) &&
0882         (strcmp(dev->parent->dev->drv->name, "AMBAPP_LEON2_DRV") != 0)) {
0883         /* We only support GRPCI2 driver on local bus */
0884         return DRVMGR_FAIL;
0885     }
0886 
0887     priv = dev->priv;
0888     if (!priv)
0889         return DRVMGR_NOMEM;
0890 
0891     priv->dev = dev;
0892     grpci2priv = priv;
0893 
0894     /* Initialize GRPCI2 Hardware */
0895     status = grpci2_init(priv);
0896     if (status) {
0897         printk("Failed to initialize grpci2 driver %d\n", status);
0898         return -1;
0899     }
0900 
0901     /* Register the PCI core at the PCI layers */
0902 
0903     if (priv->bt_enabled == 0) {
0904         /* Host is Big-Endian */
0905         pci_endian = PCI_BIG_ENDIAN;
0906 
0907         memcpy(&grpci2_access_drv.io, &grpci2_io_ops_be,
0908                         sizeof(grpci2_io_ops_be));
0909         grpci2_access_drv.memreg = &pci_memreg_sparc_be_ops;
0910     }
0911 
0912     if (pci_access_drv_register(&grpci2_access_drv)) {
0913         /* Access routines registration failed */
0914         return DRVMGR_FAIL;
0915     }
0916 
0917     /* Prepare memory MAP */
0918     grpci2_auto_cfg.options = 0;
0919     grpci2_auto_cfg.mem_start = 0;
0920     grpci2_auto_cfg.mem_size = 0;
0921     grpci2_auto_cfg.memio_start = priv->pci_area;
0922     grpci2_auto_cfg.memio_size = priv->pci_area_end - priv->pci_area;
0923     grpci2_auto_cfg.io_start = 0x100; /* avoid PCI address 0 */
0924     grpci2_auto_cfg.io_size = 0x10000 - 0x100; /* lower 64kB I/O 16 */
0925     grpci2_auto_cfg.irq_map = grpci2_bus0_irq_map;
0926     grpci2_auto_cfg.irq_route = NULL; /* use standard routing */
0927     pci_config_register(&grpci2_auto_cfg);
0928 
0929     if (pci_config_init()) {
0930         /* PCI configuration failed */
0931         return DRVMGR_FAIL;
0932     }
0933 
0934     /* Initialize/Register Driver Manager PCI Bus */
0935     priv->config.maps_down = &priv->maps_down[0];
0936     priv->config.maps_up = &priv->maps_up[0];
0937     return pcibus_register(dev, &priv->config);
0938 }
0939 
0940 int grpci2_init3(struct drvmgr_dev *dev)
0941 {
0942     struct grpci2_priv *priv = dev->priv;
0943 
0944     /* Install and Enable PCI Error interrupt handler */
0945     drvmgr_interrupt_register(dev, 0, "grpci2", grpci2_err_isr, priv);
0946 
0947     /* Initialize DMA driver (if supported) */
0948     if (priv->regs->sts_cap & STS_DMA){
0949         grpci2dma_init((void *) &(priv->regs->dma_ctrl), grpci2_dma_isr_register);
0950     }
0951 
0952     /* Unmask Error IRQ and all PCI interrupts at PCI Core. For this to be
0953      * safe every PCI board have to be resetted (no IRQ generation) before
0954      * Global IRQs are enabled (Init is reached or similar)
0955      */
0956     priv->regs->ctrl |= (CTRL_EI | priv->irq_mask);
0957 
0958     return DRVMGR_OK;
0959 }
0960 
0961 static void grpci2_dma_isr_register( void (*isr)(void *), void * arg)
0962 {
0963     struct grpci2_priv *priv = grpci2priv;
0964 
0965     /* Handle unregistration */
0966     if (priv->dma_isr != NULL) {
0967         drvmgr_interrupt_unregister(priv->dev, priv->irq_dma, grpci2_dma_isr, priv);
0968         /* Uninstall user ISR */
0969         priv->dma_isr = NULL;
0970         priv->dma_isr_arg = NULL;
0971     }
0972 
0973     if (isr == NULL)
0974         return;
0975 
0976     /* Install user ISR */
0977     priv->dma_isr_arg = arg;
0978     priv->dma_isr = isr;
0979 
0980     /* Install and Enable PCI DMA interrupt handler */
0981     if (priv->irq_mode == 1) {
0982         priv->irq_dma = 1;
0983     } else if (priv->irq_mode == 3) {
0984         priv->irq_dma = 4;
0985     } else {
0986         priv->irq_dma = 0;
0987     }
0988     drvmgr_interrupt_register(priv->dev, priv->irq_dma, "grpci2dma", grpci2_dma_isr, priv);
0989 }
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