dev/irq/arm-gicv2-zynqmp.c

0001 /* SPDX-License-Identifier: BSD-2-Clause */
0002
0003 /**
0004  * @file
0005  *
0006  * @ingroup DevIRQGIC
0007  *
0008  * @brief This source file contains the implementation of
0009  *   bsp_interrupt_get_attributes() for the GICv2 of Xilinx Zynq UltraScale+
0010  *   MPSoC and RFSoC devices.
0011  */
0012
0013 /*
0014  * Copyright (C) 2021 On-Line Applications Research Corporation (OAR)
0015  * Written by Kinsey Moore <kinsey.moore@oarcorp.com>
0016  *
0017  * Redistribution and use in source and binary forms, with or without
0018  * modification, are permitted provided that the following conditions
0019  * are met:
0020  * 1. Redistributions of source code must retain the above copyright
0021  *    notice, this list of conditions and the following disclaimer.
0022  * 2. Redistributions in binary form must reproduce the above copyright
0023  *    notice, this list of conditions and the following disclaimer in the
0024  *    documentation and/or other materials provided with the distribution.
0025  *
0026  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
0027  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
0028  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
0029  * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
0030  * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
0031  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
0032  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
0033  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
0034  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
0035  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
0036  * POSSIBILITY OF SUCH DAMAGE.
0037  */
0038
0039 #include <dev/irq/arm-gic.h>
0040 #include <bsp/irq-generic.h>
0041
0042 rtems_status_code bsp_interrupt_get_attributes(
0043   rtems_vector_number         vector,
0044   rtems_interrupt_attributes *attributes
0045 )
0046 {
0047   attributes->is_maskable = true;
0048   attributes->maybe_enable = true;
0049   attributes->maybe_disable = true;
0050   attributes->can_raise = true;
0051   attributes->can_get_priority = true;
0052   attributes->can_set_priority = true;
0053   attributes->maximum_priority = 255;
0054
0055   if ( vector <= ARM_GIC_IRQ_SGI_LAST ) {
0056     /*
0057      * It is implementation-defined whether implemented SGIs are permanently
0058      * enabled, or can be enabled and disabled by writes to GICD_ISENABLER0 and
0059      * GICD_ICENABLER0.
0060      */
0061     attributes->can_raise_on = true;
0062     attributes->cleared_by_acknowledge = true;
0063     attributes->trigger_signal = RTEMS_INTERRUPT_NO_SIGNAL;
0064   } else {
0065     attributes->can_disable = true;
0066     attributes->can_clear = true;
0067     attributes->trigger_signal = RTEMS_INTERRUPT_UNSPECIFIED_SIGNAL;
0068
0069     /*
0070      * Interrupt 67 affinity value presents as unimplemented in the
0071      * configuration of the GICv2 instance used in ZynqMP CPUs.
0072      */
0073     if ( vector > ARM_GIC_IRQ_PPI_LAST && vector != 67 ) {
0074       /* SPI */
0075       attributes->can_get_affinity = true;
0076       attributes->can_set_affinity = true;
0077     }
0078   }
0079
0080   return RTEMS_SUCCESSFUL;
0081 }