dev/irq/arm-gicv2-get-attributes.c

0001 /* SPDX-License-Identifier: BSD-2-Clause */
0002
0003 /**
0004  * @file
0005  *
0006  * @ingroup DevIRQGIC
0007  *
0008  * @brief This source file contains the implementation of
0009  *   bsp_interrupt_get_attributes() for the GICv2.
0010  */
0011
0012 /*
0013  * Copyright (C) 2013, 2021 embedded brains GmbH & Co. KG
0014  *
0015  * Redistribution and use in source and binary forms, with or without
0016  * modification, are permitted provided that the following conditions
0017  * are met:
0018  * 1. Redistributions of source code must retain the above copyright
0019  *    notice, this list of conditions and the following disclaimer.
0020  * 2. Redistributions in binary form must reproduce the above copyright
0021  *    notice, this list of conditions and the following disclaimer in the
0022  *    documentation and/or other materials provided with the distribution.
0023  *
0024  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
0025  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
0026  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
0027  * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
0028  * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
0029  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
0030  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
0031  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
0032  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
0033  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
0034  * POSSIBILITY OF SUCH DAMAGE.
0035  */
0036
0037 #include <dev/irq/arm-gic.h>
0038 #include <bsp/irq-generic.h>
0039
0040 rtems_status_code bsp_interrupt_get_attributes(
0041   rtems_vector_number         vector,
0042   rtems_interrupt_attributes *attributes
0043 )
0044 {
0045   attributes->is_maskable = true;
0046   attributes->maybe_enable = true;
0047   attributes->maybe_disable = true;
0048   attributes->can_raise = true;
0049   attributes->can_get_priority = true;
0050   attributes->can_set_priority = true;
0051   attributes->maximum_priority = 255;
0052
0053   if ( vector <= ARM_GIC_IRQ_SGI_LAST ) {
0054     /*
0055      * It is implementation-defined whether implemented SGIs are permanently
0056      * enabled, or can be enabled and disabled by writes to GICD_ISENABLER0 and
0057      * GICD_ICENABLER0.
0058      */
0059     attributes->can_raise_on = true;
0060     attributes->cleared_by_acknowledge = true;
0061     attributes->trigger_signal = RTEMS_INTERRUPT_NO_SIGNAL;
0062   } else {
0063     attributes->can_disable = true;
0064     attributes->can_clear = true;
0065     attributes->trigger_signal = RTEMS_INTERRUPT_UNSPECIFIED_SIGNAL;
0066
0067     if ( vector > ARM_GIC_IRQ_PPI_LAST ) {
0068       /* SPI */
0069       attributes->can_get_affinity = true;
0070       attributes->can_set_affinity = true;
0071     }
0072   }
0073
0074   return RTEMS_SUCCESSFUL;
0075 }