dev/clock/xil-ttc.c

0001 /* SPDX-License-Identifier: BSD-2-Clause */
0002
0003 /**
0004  * @file
0005  *
0006  * @ingroup RTEMSDriverClockXilTTC
0007  *
0008  * @brief This source file contains a Clock Driver implementation using the
0009  *   Xilinx Triple Timer Counter (TTC).
0010  */
0011
0012 /*
0013  * Copyright (C) 2024 embedded brains GmbH & Co. KG
0014  * Copyright (C) 2023 Reflex Aerospace GmbH
0015  *
0016  * Written by Philip Kirkpatrick <p.kirkpatrick@reflexaerospace.com>
0017  *
0018  * Redistribution and use in source and binary forms, with or without
0019  * modification, are permitted provided that the following conditions
0020  * are met:
0021  * 1. Redistributions of source code must retain the above copyright
0022  *    notice, this list of conditions and the following disclaimer.
0023  * 2. Redistributions in binary form must reproduce the above copyright
0024  *    notice, this list of conditions and the following disclaimer in the
0025  *    documentation and/or other materials provided with the distribution.
0026  *
0027  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
0028  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
0029  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
0030  * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
0031  * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
0032  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
0033  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
0034  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
0035  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
0036  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
0037  * POSSIBILITY OF SUCH DAMAGE.
0038  */
0039
0040 #include <bsp.h>
0041 #include <bsp/irq-generic.h>
0042 #include <bsp/fatal.h>
0043 #include <dev/clock/xttcps_hw.h>
0044 #include <rtems/sysinit.h>
0045 #include <rtems/timecounter.h>
0046 #include <rtems/score/processormaskimpl.h>
0047
0048 #if XTTCPS_COUNT_VALUE_MASK != UINT32_MAX
0049 #error "unexpected XTTCPS_COUNT_VALUE_MASK value"
0050 #endif
0051
0052 /**
0053  * @defgroup RTEMSDriverClockXilTTC \
0054  *   Xilinx Triple Timer Counter (TTC) Clock Driver
0055  *
0056  * @ingroup RTEMSDriverClockImpl
0057  *
0058  * @brief This group contains the Xilinx Triple Timer Counter (TTC) Clock
0059  *   Driver implementation.
0060  *
0061  * @{
0062  */
0063
0064 uint32_t _CPU_Counter_frequency( void )
0065 {
0066   return XIL_CLOCK_TTC_REFERENCE_CLOCK;
0067 }
0068
0069 CPU_Counter_ticks _CPU_Counter_read(void)
0070 {
0071   return XTtcPs_ReadReg(XIL_CLOCK_TTC_BASE_ADDR, XTTCPS_COUNT_VALUE_OFFSET);
0072 }
0073
0074 static void xil_ttc_initialize(void)
0075 {
0076   /* Do not use a prescaler to get a high resolution time source */
0077   XTtcPs_WriteReg(XIL_CLOCK_TTC_BASE_ADDR, XTTCPS_CLK_CNTRL_OFFSET, 0);
0078
0079   /* Disable interupts */
0080   XTtcPs_WriteReg(XIL_CLOCK_TTC_BASE_ADDR, XTTCPS_IER_OFFSET, 0);
0081
0082   /*
0083    * Enable the timer, do not enable waveform output, increment up, use
0084    * overflow mode, enable match mode.
0085    */
0086   XTtcPs_WriteReg(XIL_CLOCK_TTC_BASE_ADDR, XTTCPS_CNT_CNTRL_OFFSET,
0087                   XTTCPS_CNT_CNTRL_EN_WAVE_MASK | XTTCPS_CNT_CNTRL_MATCH_MASK);
0088 }
0089
0090 RTEMS_SYSINIT_ITEM(
0091   xil_ttc_initialize,
0092   RTEMS_SYSINIT_CPU_COUNTER,
0093   RTEMS_SYSINIT_ORDER_MIDDLE
0094 );
0095
0096 typedef struct {
0097   struct timecounter base;
0098   uint32_t irq_match_interval;
0099 } xil_ttc_timecounter;
0100
0101 static xil_ttc_timecounter xil_ttc_clock_instance;
0102
0103 static uint32_t xil_ttc_get_timecount(struct timecounter *tc)
0104 {
0105   (void) tc;
0106   return XTtcPs_ReadReg(XIL_CLOCK_TTC_BASE_ADDR, XTTCPS_COUNT_VALUE_OFFSET);
0107 }
0108
0109 static void xil_ttc_clock_driver_support_initialize_hardware(void)
0110 {
0111   xil_ttc_timecounter *tc;
0112   uint64_t frequency;
0113   uint32_t irq_match_interval;
0114   uint32_t count;
0115
0116   tc = &xil_ttc_clock_instance;
0117   frequency = XIL_CLOCK_TTC_REFERENCE_CLOCK;
0118   irq_match_interval = (uint32_t)
0119     ((frequency * rtems_configuration_get_microseconds_per_tick()) / 1000000);
0120
0121   /* Setup match register to generate clock interrupts */
0122   count = XTtcPs_ReadReg(XIL_CLOCK_TTC_BASE_ADDR, XTTCPS_COUNT_VALUE_OFFSET);
0123   XTtcPs_WriteReg(XIL_CLOCK_TTC_BASE_ADDR, XTTCPS_MATCH_0_OFFSET,
0124                   count + irq_match_interval);
0125
0126   /* Clear interupts (clear on read) */
0127   (void) XTtcPs_ReadReg(XIL_CLOCK_TTC_BASE_ADDR, XTTCPS_ISR_OFFSET);
0128
0129   /* Enable interupt for match register */
0130   XTtcPs_WriteReg(XIL_CLOCK_TTC_BASE_ADDR, XTTCPS_IER_OFFSET,
0131                   XTTCPS_IXR_MATCH_0_MASK);
0132
0133   /* Install timecounter */
0134   tc->irq_match_interval = irq_match_interval;
0135   tc->base.tc_counter_mask = UINT32_MAX;
0136   tc->base.tc_frequency = XIL_CLOCK_TTC_REFERENCE_CLOCK;
0137   tc->base.tc_get_timecount = xil_ttc_get_timecount;
0138   tc->base.tc_quality = RTEMS_TIMECOUNTER_QUALITY_CLOCK_DRIVER;
0139   rtems_timecounter_install(&tc->base);
0140 }
0141
0142 static void xil_ttc_clock_driver_support_at_tick(xil_ttc_timecounter *tc)
0143 {
0144   uint32_t irq_match_interval;
0145   uint32_t count;
0146   uint32_t match;
0147
0148   irq_match_interval = tc->irq_match_interval;
0149
0150   /* Update match register */
0151   match = XTtcPs_ReadReg(XIL_CLOCK_TTC_BASE_ADDR, XTTCPS_MATCH_0_OFFSET);
0152   match += irq_match_interval;
0153   XTtcPs_WriteReg(XIL_CLOCK_TTC_BASE_ADDR, XTTCPS_MATCH_0_OFFSET, match);
0154
0155   /* Clear interupts (clear on read) */
0156   (void) XTtcPs_ReadReg(XIL_CLOCK_TTC_BASE_ADDR, XTTCPS_ISR_OFFSET);
0157
0158   /* Check that the new match value is in the future */
0159   count = XTtcPs_ReadReg(XIL_CLOCK_TTC_BASE_ADDR, XTTCPS_COUNT_VALUE_OFFSET);
0160
0161   while (RTEMS_PREDICT_FALSE(match - count > irq_match_interval)) {
0162     /*
0163      * Tick misses may happen if interrupts are disabled for an extremly long
0164      * period or while debugging.
0165      */
0166     rtems_timecounter_tick();
0167
0168     /* Update match register */
0169     match += irq_match_interval;
0170     XTtcPs_WriteReg(XIL_CLOCK_TTC_BASE_ADDR, XTTCPS_MATCH_0_OFFSET, match);
0171
0172     /* Clear interupts (clear on read) */
0173     (void) XTtcPs_ReadReg(XIL_CLOCK_TTC_BASE_ADDR, XTTCPS_ISR_OFFSET);
0174
0175     /* Maybe the new match value is now in the future */
0176     count = XTtcPs_ReadReg(XIL_CLOCK_TTC_BASE_ADDR, XTTCPS_COUNT_VALUE_OFFSET);
0177   }
0178 }
0179
0180 static rtems_interrupt_entry xil_ttc_interrupt_entry;
0181
0182 static void xil_ttc_clock_driver_support_install_isr(
0183   rtems_interrupt_handler handler
0184 )
0185 {
0186   rtems_status_code sc;
0187
0188 #if !defined(ZYNQMP_RPU_LOCK_STEP_MODE) && ZYNQMP_RPU_SPLIT_INDEX != 0
0189   Processor_mask affinity;
0190   _Processor_mask_From_uint32_t(
0191     &affinity,
0192     UINT32_C(1) << ZYNQMP_RPU_SPLIT_INDEX,
0193     0
0194   );
0195   (void) bsp_interrupt_set_affinity(XIL_CLOCK_TTC_IRQ, &affinity);
0196 #endif
0197
0198   rtems_interrupt_entry_initialize(
0199     &xil_ttc_interrupt_entry,
0200     handler,
0201     &xil_ttc_clock_instance,
0202     "Clock"
0203   );
0204   sc = rtems_interrupt_entry_install(
0205     XIL_CLOCK_TTC_IRQ,
0206     RTEMS_INTERRUPT_UNIQUE,
0207     &xil_ttc_interrupt_entry
0208   );
0209   if ( sc != RTEMS_SUCCESSFUL ) {
0210     bsp_fatal(XIL_FATAL_TTC_IRQ_INSTALL);
0211   }
0212 }
0213
0214 #define Clock_driver_support_at_tick(arg) \
0215   xil_ttc_clock_driver_support_at_tick(arg)
0216
0217 #define Clock_driver_support_initialize_hardware \
0218   xil_ttc_clock_driver_support_initialize_hardware
0219
0220 #define Clock_driver_support_install_isr(isr) \
0221   xil_ttc_clock_driver_support_install_isr(isr)
0222
0223 /** @} */
0224
0225 #include "../../../shared/dev/clock/clockimpl.h"