gensh4/start/start.S

0001 /*
0002  * start.S -- Initialization code for SH7750 generic BSP
0003  *
0004  * Copyright (C) 2001 OKTET Ltd., St.-Petersburg, Russia
0005  * Author: Victor V. Vengerov <vvv@oktet.ru>
0006  *
0007  * Based on work:
0008  *  Authors: Ralf Corsepius (corsepiu@faw.uni-ulm.de) and
0009  *           Bernd Becker (becker@faw.uni-ulm.de)
0010  *
0011  *  COPYRIGHT (c) 1997-1998, FAW Ulm, Germany
0012  *
0013  *  This program is distributed in the hope that it will be useful,
0014  *  but WITHOUT ANY WARRANTY; without even the implied warranty of
0015  *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
0016  *
0017  *  Modified to reflect Hitachi EDK SH7045F:
0018  *  John M. Mills (jmills@tga.com)
0019  *  TGA Technologies, Inc.
0020  *  100 Pinnacle Way, Suite 140
0021  *  Norcross, GA 30071 U.S.A.
0022  *
0023  *
0024  *  This modified file may be copied and distributed in accordance
0025  *  the above-referenced license. It is provided for critique and
0026  *  developmental purposes without any warranty nor representation
0027  *  by the authors or by TGA Technologies.
0028  *
0029  *  COPYRIGHT (c) 1999-2001.
0030  *  On-Line Applications Research Corporation (OAR).
0031  *
0032  *  The license and distribution terms for this file may be
0033  *  found in the file LICENSE in this distribution or at
0034  *  http://www.rtems.org/license/LICENSE.
0035  */
0036
0037 #include <rtems/asm.h>
0038 #include "rtems/score/sh4_regs.h"
0039 #include "rtems/score/sh7750_regs.h"
0040
0041         BEGIN_CODE
0042         PUBLIC(start)
0043
0044 /*
0045  * Algorithm of the first part of the start():
0046  *
0047  * 1. Initialize stack
0048  * 2. Are we from reset or from gdb? Set value for boot_mode in r9.
0049  * 3. Initialize hardware if we are from reset. Cache is off.
0050  * 4. Copy data from flash to ram; set up boot mode and jump to real address.
0051  * 5. Zero out bss.
0052  * 6. Turn memory cach on.
0053  */
0054
0055 SYM (start):
0056         ! install the stack pointer
0057         mov.l   stack_k,r15
0058
0059         mov.l   initial_sr_k,r0
0060         ldc     r0,ssr
0061         ldc     r0,sr
0062
0063         ! let us see if we are from gdb stub or from power-on reset
0064         bsr     fake_func
0065         nop
0066 fake_func:
0067
0068         sts     pr, r0
0069         shlr8   r0
0070         mov.l   reset_pc_value_shift_8_k, r1
0071         cmp/eq  r0, r1
0072         movt    r9      ! r9 == ! boot_mode
0073         neg     r9, r9
0074         add     #1, r9  ! r9 == boot_mode
0075
0076         ! what is in boot_mode?
0077         cmp/pl  r9      ! r9 > 0  ->  T = 1
0078
0079         ! if boot_mode != SH4_BOOT_MODE_FLASH
0080         bt      hw_init_end
0081         nop
0082
0083 #if START_HW_INIT   /* from $RTEMS_BSP.cfg */
0084         ! Initialize minimal hardware
0085         ! to run hw_init we need to calculate its address
0086         ! as it is before data copying
0087         mov.l   hw_init_k, r0
0088         mov.l   copy_start_k, r1
0089         mov.l   copy_end_k, r2
0090         cmp/ge  r0, r1
0091         bt      0f
0092         cmp/ge  r0, r2
0093         bf      0f
0094         ! if  copy_start <= hw_init <= copy_end  then
0095         neg     r1, r1
0096         mov.l   copy_start_in_rom_k, r3
0097         add     r1,r0
0098         add     r3, r0
0099 0:
0100         jsr @r0
0101         nop     !delay slot
0102 #endif /* START_HW_INIT */
0103 hw_init_end:
0104
0105 #if COPY_DATA_FROM_ROM
0106         ! copy data from rom to ram
0107         mov.l   copy_start_k, r0
0108         mov.l   copy_end_k, r1
0109         mov.l   copy_start_in_rom_k, r2
0110
0111         ! if copy_from == copy_to do not copy anything
0112         cmp/eq  r0, r2
0113         bt      real_address
0114         nop
0115
0116 copy_data_cycle:
0117         cmp/ge  r1, r0
0118         bt      end_of_copy_data_cycle
0119         nop
0120         mov.l   @r2+, r3
0121         mov.l   r3, @r0
0122         add     #4, r0
0123         bra     copy_data_cycle
0124         nop
0125
0126 end_of_copy_data_cycle:
0127 #endif
0128         ! go to 0x8....... adresses
0129         mov.l   real_address_k, r0
0130         lds     r0, pr
0131         rts
0132         nop
0133 real_address:
0134         ! write boot_mode to ram
0135         mov.l   boot_mode_k, r5
0136         mov.l   r9, @r5
0137
0138 zero_bss:
0139         ! zero out bss
0140         mov.l   __bss_start_k,r0
0141         mov.l   __bss_end_k,r1
0142         mov #0,r2
0143 0:
0144         mov.l   r2,@r0
0145         add #4,r0
0146         cmp/ge  r0,r1
0147         bt  0b
0148         nop
0149
0150         ! Turn cache on
0151         mov.l   cache_on_k, r0
0152         jsr @r0
0153         nop     !delay slot
0154
0155         ! Save old value of VBR register. We will need it to allow
0156         ! debugger agent hook exceptions.
0157         mov.l   __VBR_Saved_k,r0
0158         stc     vbr,r5
0159         mov.l   r5,@r0
0160         ! Set up VBR register
0161         mov.l   _vbr_base_k,r0
0162         ldc     r0,vbr
0163
0164         ! initialise fpscr for gcc
0165         mov.l set_fpscr_k, r1
0166         jsr @r1
0167         nop
0168
0169         ! Set FPSCR register
0170         mov.l   initial_fpscr_k,r0
0171         lds     r0,fpscr
0172
0173         ! call the mainline
0174         mov #0,r4       ! argc
0175         mov.l main_k,r0
0176         jsr @r0
0177         nop
0178
0179         ! call exit
0180         mov r0,r4
0181         mov.l   exit_k,r0
0182         jsr @r0
0183         or  r0,r0
0184
0185         .global _stop
0186 _stop:
0187         mov     #11,r0
0188         mov     #0,r4
0189         trapa   #0x3f
0190         nop
0191 __stop:
0192         bra     __stop
0193         nop
0194
0195         END_CODE
0196
0197         .align 2
0198 #if START_HW_INIT
0199 copy_start_k:
0200         .long copy_start
0201 copy_end_k:
0202         .long copy_end
0203 #endif
0204 #if COPY_DATA_FROM_ROM
0205 copy_start_in_rom_k:
0206         .long copy_start_in_rom
0207 #endif
0208
0209 real_address_k:
0210         .long real_address
0211 set_fpscr_k:
0212     .long   ___set_fpscr
0213 _vbr_base_k:
0214         .long   SYM(_vbr_base)
0215 __VBR_Saved_k:
0216         .long   SYM(_VBR_Saved)
0217 stack_k:
0218         .long   SYM(_ISR_Stack_area_end)
0219 __bss_start_k:
0220         .long   __bss_start
0221 __bss_end_k:
0222         .LONG   __bss_end
0223 main_k:
0224         .long   SYM(boot_card)
0225 exit_k:
0226         .long   SYM(_exit)
0227
0228 #if START_HW_INIT   /* from $RTEMS_BSP.cfg */
0229 hw_init_k:
0230         .long   SYM(early_hw_init)
0231 #endif /* START_HW_INIT */
0232
0233 cache_on_k:
0234         .long   SYM(bsp_cache_on)
0235
0236 vects_k:
0237         .long   SYM(vectab)
0238 vects_size:
0239         .word   255
0240
0241     .align 2
0242 initial_sr_k:
0243         .long   SH4_SR_MD | SH4_SR_IMASK
0244 initial_fpscr_k:
0245 #ifdef __SH4__
0246         .long   SH4_FPSCR_DN | SH4_FPSCR_PR | SH4_FPSCR_RM
0247 #else
0248         .long   SH4_FPSCR_DN | SH4_FPSCR_RM
0249 #endif
0250
0251 reset_pc_value_shift_8_k:
0252         .long   0xa00000
0253
0254 boot_mode_k:
0255         .long   _boot_mode
0256
0257 #ifdef __ELF__
0258         .section .bss,"aw"
0259 #else
0260         .section .bss
0261 #endif
0262
0263         .global __sh4sim_dummy_register
0264 __sh4sim_dummy_register:
0265         .long   0
0266
0267         .section    .data
0268         .global _boot_mode
0269 _boot_mode:
0270         .long   0