gensh4/start/hw_init.c

0001 /*
0002  * SMFD board hardware initialization.
0003  */
0004
0005 /*
0006  * Copyright (C) 2001 OKTET Ltd., St.-Petersburg, Russia
0007  * Author: Victor V. Vengerov <vvv@oktet.ru>
0008  *         Alexandra Kossovsky <sasha@oktet.ru>
0009  *
0010  *  The license and distribution terms for this file may be
0011  *  found in the file LICENSE in this distribution or at
0012  *  http://www.rtems.org/license/LICENSE.
0013  */
0014
0015 #include "rtems/score/sh7750_regs.h"
0016 #include "rtems/score/sh_io.h"
0017 #include "sdram.h"
0018 #include "bsp.h"
0019
0020 /* early_hw_init --
0021  *     Perform initial hardware initialization:
0022  *         - setup clock generator
0023  *         - initialize bus state controller, memory settings, SDRAM
0024  *         - disable DMA
0025  *         - setup external ports, etc.
0026  *         - initialize interrupt controller
0027  *
0028  *     This function should not access the memory! It should be compiled
0029  *     with -fomit-frame-pointer to avoid stack access.
0030  */
0031 void early_hw_init(void)
0032 {
0033   /* Explicitly turn off the MMU */
0034   write32(0, SH7750_MMUCR);
0035
0036   /* Disable instruction and operand caches */
0037   write32(0, SH7750_CCR);
0038
0039   /* Setup Clock Generator */
0040   /*
0041    * Input clock frequency is 16 MHz, MD0=1,
0042    * CPU clock frequency already selected to 96MHz.
0043    * Bus clock frequency should be set to 48 MHz, therefore divider 2
0044    * should be applied (bus frequency is 48 MHz, clock period is 20.84ns).
0045    * Peripheral frequency should be set to 24 MHz, therefore divider 4
0046    * should be used.
0047    */
0048   /* Prepare watchdog timer for frequency changing */
0049   write16((read8(SH7750_WTCSR) & ~SH7750_WTCSR_TME) |
0050           SH7750_WTCSR_KEY, SH7750_WTCSR);
0051   write16(SH7750_WTCSR_MODE_IT | SH7750_WTCSR_CKS_DIV4096 |
0052           SH7750_WTCSR_KEY, SH7750_WTCSR);
0053
0054   /* Turn PLL1 on */
0055   write16(0x40 | SH7750_WTCNT_KEY, SH7750_WTCNT);
0056   write16(read16(SH7750_FRQCR) | SH7750_FRQCR_PLL1EN, SH7750_FRQCR);
0057
0058   /* Perform Frequency Selection */
0059   write16(0x40 | SH7750_WTCNT_KEY, SH7750_WTCNT);
0060   write16(SH7750_FRQCR_CKOEN | SH7750_FRQCR_PLL1EN |
0061           SH7750_FRQCR_IFCDIV1 | SH7750_FRQCR_BFCDIV2 | SH7750_FRQCR_PFCDIV4,
0062           SH7750_FRQCR);
0063
0064   /* Turn PLL2 on */
0065   write16(0x40 | SH7750_WTCNT_KEY, SH7750_WTCNT);
0066   write16(read16(SH7750_FRQCR) | SH7750_FRQCR_PLL2EN, SH7750_FRQCR);
0067
0068   /* Bus State Controller Initialization */
0069   /*
0070    * Area assignments:
0071    *     Area 0: Flash memory, SRAM interface
0072    *     Area 1: GDC
0073    *     Area 2: SDRAM
0074    *     Area 3-6: unused
0075    */
0076   write32(
0077       /* Pull-ups (IPUP, OPUP) enabled */
0078       /* No Byte-Control SRAM mode for Area 1 and Area 3 */
0079       SH7750_BCR1_BREQEN | /* Enable external bus requests */
0080       /* No Partial Sharing Mode */
0081       /* No MPX interface */
0082       /* Memory and Control Signals are in HiZ */
0083       SH7750_BCR1_A0BST_SRAM | /* No burst ROM in flash */
0084       SH7750_BCR1_A5BST_SRAM | /* Area 5 is not in use */
0085       SH7750_BCR1_A6BST_SRAM | /* Area 6 is not in use */
0086       SH7750_BCR1_DRAMTP_2SDRAM_3SDRAM  /* Select Area 2 SDRAM type */
0087       /* Area 5,6 programmed as a SRAM interface (not PCMCIA) */,
0088       SH7750_BCR1);
0089
0090   write16(
0091       (SH7750_BCR2_SZ_8 << SH7750_BCR2_A0SZ_S) |  /* These bits is read-only
0092                                                      and set during reset */
0093       (SH7750_BCR2_SZ_32 << SH7750_BCR2_A6SZ_S) | /* Area 6 not used */
0094       (SH7750_BCR2_SZ_32 << SH7750_BCR2_A5SZ_S) | /* Area 5 not used */
0095       (SH7750_BCR2_SZ_32 << SH7750_BCR2_A4SZ_S) | /* Area 4 not used */
0096       (SH7750_BCR2_SZ_32 << SH7750_BCR2_A3SZ_S) | /* Area 3 not used */
0097       (SH7750_BCR2_SZ_32 << SH7750_BCR2_A2SZ_S) | /* SDRAM is 32-bit width */
0098       (SH7750_BCR2_SZ_32 << SH7750_BCR2_A1SZ_S) | /* GDC is 32-bit width */
0099       SH7750_BCR2_PORTEN,                         /* Use D32-D51 as a port */
0100       SH7750_BCR2);
0101
0102   write32(
0103       (0 << SH7750_WCR1_DMAIW_S) |  /* 0 required for SDRAM RAS down mode */
0104       (7 << SH7750_WCR1_A6IW_S) |   /* Area 6 not used */
0105       (7 << SH7750_WCR1_A5IW_S) |   /* Area 5 not used */
0106       (7 << SH7750_WCR1_A4IW_S) |   /* Area 4 not used */
0107       (7 << SH7750_WCR1_A3IW_S) |   /* Area 3 not used */
0108       (1 << SH7750_WCR1_A2IW_S) |   /* 1 idle cycles inserted between acc */
0109       (7 << SH7750_WCR1_A1IW_S) |   /* Don't have GDC specs... Set safer. */
0110       (1 << SH7750_WCR1_A0IW_S),    /* 1 idle cycles inserted between acc */
0111       SH7750_WCR1);
0112
0113   write32(
0114       (SH7750_WCR2_WS15   << SH7750_WCR2_A6W_S) | /* Area 6 not used */
0115       (SH7750_WCR2_BPWS7  << SH7750_WCR2_A6B_S) |
0116       (SH7750_WCR2_WS15   << SH7750_WCR2_A5W_S) | /* Area 5 not used */
0117       (SH7750_WCR2_BPWS7  << SH7750_WCR2_A5B_S) |
0118       (SH7750_WCR2_WS15   << SH7750_WCR2_A4W_S) | /* Area 4 not used */
0119       (SH7750_WCR2_WS15   << SH7750_WCR2_A3W_S) | /*Area 3 not used*/
0120       (SH7750_WCR2_SDRAM_CAS_LAT2 << SH7750_WCR2_A2W_S) | /* SDRAM CL = 2 */
0121       (SH7750_WCR2_WS15   << SH7750_WCR2_A1W_S) | /* Area 1 (GDC)
0122                                                      requirements not known*/
0123       (SH7750_WCR2_WS6    << SH7750_WCR2_A0W_S) | /* 4 wait states required
0124                                                      at 48MHz for 70ns mem.,
0125                                                      set closest greater */
0126       (SH7750_WCR2_BPWS7  << SH7750_WCR2_A0B_S),  /* burst mode disabled for
0127                                                      Area 0 flash ROM */
0128       SH7750_WCR2);
0129   write32(
0130       SH7750_WCR3_A6S |                           /* Area 6 not used */
0131       (SH7750_WCR3_DHWS_3 << SH7750_WCR3_A6H_S) |
0132       SH7750_WCR3_A5S |                           /* Area 5 not used */
0133       (SH7750_WCR3_DHWS_3 << SH7750_WCR3_A5H_S) |
0134       SH7750_WCR3_A4S |                           /* Area 4 not used */
0135       (SH7750_WCR3_DHWS_3 << SH7750_WCR3_A4H_S) |
0136       SH7750_WCR3_A3S |                           /* Area 3 not used */
0137       (SH7750_WCR3_DHWS_3 << SH7750_WCR3_A3H_S) |
0138       SH7750_WCR3_A2S |                           /* SDRAM - ignored */
0139       (SH7750_WCR3_DHWS_3 << SH7750_WCR3_A2H_S) |
0140       SH7750_WCR3_A1S |                           /* GDC - unknown, set max*/
0141       (SH7750_WCR3_DHWS_3 << SH7750_WCR3_A1H_S) |
0142       0 |               /* flash ROM - no write strobe setup time required */
0143       (SH7750_WCR3_DHWS_0 << SH7750_WCR3_A0H_S),
0144       SH7750_WCR3);
0145
0146   #define MCRDEF \
0147       /* SH7750_MCR_RASD | */  /* Set RAS Down mode */                      \
0148       (SH7750_MCR_TRC_0 | SH7750_MCR_TRAS_SDRAM_TRC_4 |                     \
0149                /* RAS precharge time is 63ns; it corresponds to 4 clocks */ \
0150       /* TCAS valid only for DRAM interface */                              \
0151       SH7750_MCR_TPC_SDRAM_1 | /* TPC = 20ns = 1 clock */                   \
0152       SH7750_MCR_RCD_SDRAM_2 | /* RCD = 21ns = 2 clock */                   \
0153       /* After write, next active command is not issued for a period of     \
0154          TPC + TRWL. SDRAM specifies that it should be BL+Trp clocks when   \
0155          CL=2. Trp = 20ns = 1clock; BL=8. Therefore we should wait 9        \
0156          clocks. Don't know why, but 6 clocks (TRWL=5 and TPC=1) seems      \
0157          working. May be, something wrong in documentation? */              \
0158       SH7750_MCR_TRWL_5 |      /* TRWL = 5 clock        */                  \
0159       SH7750_MCR_BE |          /* Always enabled for SDRAM */               \
0160       SH7750_MCR_SZ_32 |       /* Memory data size is 32 bit */             \
0161       (4 << SH7750_MCR_AMX_S) | /* Select memory device type */             \
0162       SH7750_MCR_RFSH |        /* Refresh is performed */                   \
0163       SH7750_MCR_RMODE_NORMAL) /* Auto-Refresh mode */
0164
0165   /* Clear refresh timer counter */
0166   write16(SH7750_RTCNT_KEY | 0, SH7750_RTCNT);
0167
0168   /* Time between auto-refresh commands is 15.6 microseconds; refresh
0169      timer counter frequency is 12 MHz; 1.56e-5*1.2e7= 187.2, therefore
0170      program the refresh timer divider to 187 */
0171   write16(SH7750_RTCOR_KEY | 187, SH7750_RTCOR);
0172
0173   /* Clear refresh counter */
0174   write16(SH7750_RFCR_KEY | 0, SH7750_RFCR);
0175
0176   /* Select refresh counter base frequency as bus frequency/4 = 12 MHz */
0177   write16(SH7750_RTCSR_CKS_CKIO_DIV4 | SH7750_RTCSR_KEY, SH7750_RTCSR);
0178
0179   /* Initialize Memory Control Register; disable refresh */
0180   write32((MCRDEF & ~SH7750_MCR_RFSH) | SH7750_MCR_PALL, SH7750_MCR);
0181
0182   /* SDRAM power-up initialization require 100 microseconds delay after
0183      stable power and clock fed; 100 microseconds corresponds to 7 refresh
0184      intervals */
0185   while (read16(SH7750_RFCR) <= 7);
0186
0187   /* Clear refresh timer counter */
0188   write16(SH7750_RTCNT_KEY | 0, SH7750_RTCNT);
0189
0190   /* Clear refresh counter */
0191   write16(SH7750_RFCR_KEY | 0, SH7750_RFCR);
0192
0193   /* Execute Precharge All command */
0194   write32(0, SH7750_SDRAM_MODE_A2_32BIT(0));
0195
0196   /* Initialize Memory Control Register; enable refresh, prepare to
0197      SDRAM mode register setting */
0198   write32(MCRDEF | SH7750_MCR_MRSET, SH7750_MCR);
0199
0200   /* Wait until at least 2 auto-refresh commands to be executed */
0201   while (read16(SH7750_RFCR) <= 10);
0202
0203   /* SDRAM data width is 32 bit (4 bytes), cache line size is 32 bytes,
0204      therefore burst length is 8 (32 / 4) */
0205   write8(0,SH7750_SDRAM_MODE_A2_32BIT(
0206       SDRAM_MODE_BL_8 |
0207       SDRAM_MODE_BT_SEQ |    /* Only sequential burst mode supported
0208                                 in SH7750 */
0209       SDRAM_MODE_CL_2 |      /* CAS latency is 2 */
0210       SDRAM_MODE_OPC_BRBW)   /* Burst read/burst write */
0211   );
0212   /* Bus State Controller initialized now */
0213
0214   /* Disable DMA controller */
0215   write32(0, SH7750_DMAOR);
0216
0217   /* I/O port setup */
0218   /* Configure all port bits as output - to fasciliate debugging */
0219   write32(
0220       SH7750_PCTRA_PBOUT(0)  | SH7750_PCTRA_PBOUT(1) |
0221       SH7750_PCTRA_PBOUT(2)  | SH7750_PCTRA_PBOUT(3) |
0222       SH7750_PCTRA_PBOUT(4)  | SH7750_PCTRA_PBOUT(5) |
0223       SH7750_PCTRA_PBOUT(6)  | SH7750_PCTRA_PBOUT(7) |
0224       SH7750_PCTRA_PBOUT(8)  | SH7750_PCTRA_PBOUT(9) |
0225       SH7750_PCTRA_PBOUT(10) | SH7750_PCTRA_PBOUT(11) |
0226       SH7750_PCTRA_PBOUT(12) | SH7750_PCTRA_PBOUT(13) |
0227       SH7750_PCTRA_PBOUT(14) | SH7750_PCTRA_PBOUT(15),
0228       SH7750_PCTRA);
0229   write32(
0230       SH7750_PCTRB_PBOUT(16) | SH7750_PCTRB_PBOUT(17) |
0231       SH7750_PCTRB_PBOUT(18) | SH7750_PCTRB_PBOUT(19),
0232       SH7750_PCTRB);
0233   /* Clear data in port */
0234   write32(0, SH7750_PDTRA);
0235   write32(0, SH7750_PDTRB);
0236
0237   /* Interrupt Controller Initialization */
0238   write16(SH7750_ICR_IRLM, SH7750_ICR); /* IRLs serves as an independent
0239                                            interrupt request lines */
0240   /* Mask all requests at this time */
0241   write16(
0242       (0 << SH7750_IPRA_TMU0_S) |
0243       (0 << SH7750_IPRA_TMU1_S) |
0244       (0 << SH7750_IPRA_TMU2_S) |
0245       (0 << SH7750_IPRA_RTC_S),
0246       SH7750_IPRA);
0247   write16(
0248       (0 << SH7750_IPRB_WDT_S) |
0249       (0 << SH7750_IPRB_REF_S) |
0250       (0 << SH7750_IPRB_SCI1_S),
0251       SH7750_IPRB);
0252   write16(
0253       (0 << SH7750_IPRC_GPIO_S) |
0254       (0 << SH7750_IPRC_DMAC_S) |
0255       (0 << SH7750_IPRC_SCIF_S) |
0256       (0 << SH7750_IPRC_HUDI_S),
0257       SH7750_IPRC);
0258
0259 }
0260
0261 /*
0262  * cache_on --
0263  *      Enable instruction and operand caches
0264  */
0265 void bsp_cache_on(void)
0266 {
0267   switch (boot_mode) {
0268     case SH4_BOOT_MODE_FLASH:
0269       write32(SH7750_CCR_ICI | SH7750_CCR_ICE |
0270               SH7750_CCR_OCI | SH7750_CCR_CB | SH7750_CCR_OCE,
0271               SH7750_CCR);
0272       break;
0273     case SH4_BOOT_MODE_IPL:
0274       __asm__ volatile (
0275           "mov     #6, r0\n"
0276           "xor     r4, r4\n"
0277           "trapa   #0x3f\n"
0278           : : : "r0", "r4");
0279       break;
0280     default: /* unreachable */
0281       break;
0282   }
0283 }