gensh4/include/sdram.h

0001 /*
0002  * SDRAM Mode Register
0003  * Based on Fujitsu MB81F643242B data sheet.
0004  *
0005  * Copyright (C) 2001 OKTET Ltd., St.-Petersburg, Russia
0006  * Author: Victor V. Vengerov <vvv@oktet.ru>
0007  *
0008  * The license and distribution terms for this file may be
0009  * found in the file LICENSE in this distribution or at
0010  *  http://www.rtems.org/license/LICENSE.
0011  */
0012
0013 #ifndef __SDRAM_H__
0014 #define __SDRAM_H__
0015
0016 /* SDRAM Mode Register */
0017 #define SDRAM_MODE_BL         0x0007  /* Burst Length: */
0018 #define SDRAM_MODE_BL_1       0x0000  /*    0 */
0019 #define SDRAM_MODE_BL_2       0x0001  /*    2 */
0020 #define SDRAM_MODE_BL_4       0x0002  /*    4 */
0021 #define SDRAM_MODE_BL_8       0x0003  /*    8 */
0022 #define SDRAM_MODE_BL_16      0x0004  /*    16 */
0023 #define SDRAM_MODE_BL_32      0x0005  /*    32 */
0024 #define SDRAM_MODE_BL_64      0x0006  /*    64 */
0025 #define SDRAM_MODE_BL_FULL    0x0007  /*    Full column */
0026
0027 #define SDRAM_MODE_BT         0x0008  /* Burst Type: */
0028 #define SDRAM_MODE_BT_SEQ     0x0000  /*   Sequential */
0029 #define SDRAM_MODE_BT_ILV     0x0008  /*   Interleave */
0030
0031 #define SDRAM_MODE_CL         0x0070  /* CAS Latency: */
0032 #define SDRAM_MODE_CL_1       0x0010  /*    1 */
0033 #define SDRAM_MODE_CL_2       0x0020  /*    2 */
0034 #define SDRAM_MODE_CL_3       0x0030  /*    3 */
0035
0036 #define SDRAM_MODE_OPC        0x0200  /* Opcode: */
0037 #define SDRAM_MODE_OPC_BRBW   0x0000  /*     Burst read & Burst write */
0038 #define SDRAM_MODE_OPC_BRSW   0x0200  /*     Burst read & Single write */
0039
0040 #endif