rtems/score/sh4_regs.h

0001 /*
0002  * Bits on SH-4 registers.
0003  * See SH-4 Programming manual for more details.
0004  *
0005  * Copyright (C) 2001 OKTET Ltd., St.-Petersburg, Russia
0006  * Author: Alexandra Kossovsky <sasha@oktet.ru>
0007  *
0008  * The license and distribution terms for this file may be
0009  * found in the file LICENSE in this distribution or at
0010  *  http://www.rtems.org/license/LICENSE.
0011  */
0012
0013 #ifndef __SH4_REGS_H__
0014 #define __SH4_REGS_H__
0015
0016 /* SR -- Status Register */
0017 #define SH4_SR_MD          0x40000000 /* Priveleged mode */
0018 #define SH4_SR_RB          0x20000000 /* General register bank specifier */
0019 #define SH4_SR_BL          0x10000000 /* Exeption/interrupt masking bit */
0020 #define SH4_SR_FD          0x00008000 /* FPU disable bit */
0021 #define SH4_SR_M           0x00000200 /* For signed division:
0022                                          divisor (module) is negative */
0023 #define SH4_SR_Q           0x00000100 /* For signed division:
0024                                          dividend (and quotient) is negative */
0025 #define SH4_SR_IMASK       0x000000f0 /* Interrupt mask level */
0026 #define SH4_SR_IMASK_S     4
0027 #define SH4_SR_S           0x00000002 /* Saturation for MAC instruction:
0028                                          if set, data in MACH/L register
0029                                          is restricted to 48/32 bits
0030                                          for MAC.W/L instructions */
0031 #define SH4_SR_T           0x00000001 /* 1 if last condiyion was true */
0032 #define SH4_SR_RESERV      0x8fff7d0d /* Reserved bits, read/write as 0 */
0033
0034 /* FPSCR -- FPU Starus/Control Register */
0035 #define SH4_FPSCR_FR       0x00200000 /* FPU register bank specifier */
0036 #define SH4_FPSCR_SZ       0x00100000 /* FMOV 64-bit transfer mode */
0037 #define SH4_FPSCR_PR       0x00080000 /* Double-percision floating-point
0038                                          operations flag */
0039                                       /* SH4_FPSCR_SZ & SH4_FPSCR_PR != 1 */
0040 #define SH4_FPSCR_DN       0x00040000 /* Treat denormalized number as zero */
0041 #define SH4_FPSCR_CAUSE    0x0003f000 /* FPU exeption cause field */
0042 #define SH4_FPSCR_CAUSE_S  12
0043 #define SH4_FPSCR_ENABLE   0x00000f80 /* FPU exeption enable field */
0044 #define SH4_FPSCR_ENABLE_s 7
0045 #define SH4_FPSCR_FLAG     0x0000007d /* FPU exeption flag field */
0046 #define SH4_FPSCR_FLAG_S   2
0047 #define SH4_FPSCR_RM       0x00000001 /* Rounding mode:
0048                                          1/0 -- round to zero/nearest */
0049 #define SH4_FPSCR_RESERV   0xffd00000 /* Reserved bits, read/write as 0 */
0050
0051 #endif