rtems/score/ispsh7045.h

0001 /*
0002  *  This include file contains information pertaining to the Hitachi SH
0003  *  processor.
0004  *
0005  *  Authors: Ralf Corsepius (corsepiu@faw.uni-ulm.de) and
0006  *           Bernd Becker (becker@faw.uni-ulm.de)
0007  *
0008  *  COPYRIGHT (c) 1997-1998, FAW Ulm, Germany
0009  *
0010  *  This program is distributed in the hope that it will be useful,
0011  *  but WITHOUT ANY WARRANTY; without even the implied warranty of
0012  *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
0013  *
0014  *
0015  *  COPYRIGHT (c) 1998.
0016  *  On-Line Applications Research Corporation (OAR).
0017  *
0018  *  The license and distribution terms for this file may be
0019  *  found in the file LICENSE in this distribution or at
0020  *  http://www.rtems.org/license/LICENSE.
0021  *
0022  *  Modified to reflect isp entries for sh7045 processor:
0023  *  John M. Mills (jmills@tga.com)
0024  *  TGA Technologies, Inc.
0025  *  100 Pinnacle Way, Suite 140
0026  *  Norcross, GA 30071 U.S.A.
0027  *
0028  *
0029  *  This modified file may be copied and distributed in accordance
0030  *  the above-referenced license. It is provided for critique and
0031  *  developmental purposes without any warranty nor representation
0032  *  by the authors or by TGA Technologies.
0033  */
0034
0035 #ifndef __CPU_ISPS_H
0036 #define __CPU_ISPS_H
0037
0038 #ifdef __cplusplus
0039 extern "C" {
0040 #endif
0041
0042 extern void __ISR_Handler( uint32_t   vector );
0043
0044
0045 /*
0046  * interrupt vector table offsets
0047  */
0048 #define NMI_ISP_V 11
0049 #define USB_ISP_V 12
0050 #define IRQ0_ISP_V 64
0051 #define IRQ1_ISP_V 65
0052 #define IRQ2_ISP_V 66
0053 #define IRQ3_ISP_V 67
0054 #define IRQ4_ISP_V 68
0055 #define IRQ5_ISP_V 69
0056 #define IRQ6_ISP_V 70
0057 #define IRQ7_ISP_V 71
0058 #define DMA0_ISP_V 72
0059 #define DMA1_ISP_V 76
0060 #define DMA2_ISP_V 80
0061 #define DMA3_ISP_V 84
0062
0063 #define MTUA0_ISP_V 88
0064 #define MTUB0_ISP_V 89
0065 #define MTUC0_ISP_V 90
0066 #define MTUD0_ISP_V 91
0067 #define MTUV0_ISP_V 92
0068
0069 #define MTUA1_ISP_V 96
0070 #define MTUB1_ISP_V 97
0071 #define MTUV1_ISP_V 100
0072 #define MTUU1_ISP_V 101
0073
0074 #define MTUA2_ISP_V 104
0075 #define MTUB2_ISP_V 105
0076 #define MTUV2_ISP_V 108
0077 #define MTUU2_ISP_V 109
0078
0079 #define MTUA3_ISP_V 112
0080 #define MTUB3_ISP_V 113
0081 #define MTUC3_ISP_V 114
0082 #define MTUD3_ISP_V 115
0083 #define MTUV3_ISP_V 116
0084
0085 #define MTUA4_ISP_V 120
0086 #define MTUB4_ISP_V 121
0087 #define MTUC4_ISP_V 122
0088 #define MTUD4_ISP_V 123
0089 #define MTUV4_ISP_V 124
0090
0091 #define ERI0_ISP_V 128
0092 #define RXI0_ISP_V 129
0093 #define TXI0_ISP_V 130
0094 #define TEI0_ISP_V 131
0095
0096 #define ERI1_ISP_V 132
0097 #define RXI1_ISP_V 133
0098 #define TXI1_ISP_V 134
0099 #define TEI1_ISP_V 135
0100
0101 #define ADI0_ISP_V 136
0102 #define ADI1_ISP_V 137
0103 #define DTC_ISP_V 140  /* Data Transfer Controller */
0104 #define CMT0_ISP_V 144 /* Compare Match Timer */
0105 #define CMT1_ISP_V 148
0106 #define WDT_ISP_V 152  /* Wtachdog Timer */
0107 #define CMI_ISP_V 153  /* BSC RAS interrupt */
0108 #define OEI_ISP_V 156  /* I/O Port */
0109 #define DREF_ISP_V CMI_ISP_V /* DRAM Refresh from BSC */
0110 #if 0
0111 #define PRT_ISP_V /* parity error - no equivalent */
0112 #endif
0113
0114 /* dummy ISP */
0115 extern void _dummy_isp( void );
0116
0117 /* Non Maskable Interrupt */
0118 extern void _nmi_isp( void );
0119
0120 /* User Break Controller */
0121 extern void _usb_isp( void );
0122
0123 /* External interrupts 0-7 */
0124 extern void _irq0_isp( void );
0125 extern void _irq1_isp( void );
0126 extern void _irq2_isp( void );
0127 extern void _irq3_isp( void );
0128 extern void _irq4_isp( void );
0129 extern void _irq5_isp( void );
0130 extern void _irq6_isp( void );
0131 extern void _irq7_isp( void );
0132
0133 /* DMA - Controller */
0134 extern void _dma0_isp( void );
0135 extern void _dma1_isp( void );
0136 extern void _dma2_isp( void );
0137 extern void _dma3_isp( void );
0138
0139 /* Interrupt Timer Unit */
0140 /* Timer 0 */
0141 extern void _mtua0_isp( void );
0142 extern void _mtub0_isp( void );
0143 extern void _mtuc0_isp( void );
0144 extern void _mtud0_isp( void );
0145 extern void _mtuv0_isp( void );
0146 /* Timer 1 */
0147 extern void _mtua1_isp( void );
0148 extern void _mtub1_isp( void );
0149 extern void _mtuv1_isp( void );
0150 extern void _mtuu1_isp( void );
0151 /* Timer 2 */
0152 extern void _mtua2_isp( void );
0153 extern void _mtub2_isp( void );
0154 extern void _mtuv2_isp( void );
0155 extern void _mtuu2_isp( void );
0156 /* Timer 3 */
0157 extern void _mtua3_isp( void );
0158 extern void _mtub3_isp( void );
0159 extern void _mtuc3_isp( void );
0160 extern void _mtud3_isp( void );
0161 extern void _mtuv3_isp( void );
0162 /* Timer 4 */
0163 extern void _mtua4_isp( void );
0164 extern void _mtub4_isp( void );
0165 extern void _mtuc4_isp( void );
0166 extern void _mtud4_isp( void );
0167 extern void _mtuv4_isp( void );
0168
0169 /* serial interfaces */
0170 extern void _eri0_isp( void );
0171 extern void _rxi0_isp( void );
0172 extern void _txi0_isp( void );
0173 extern void _tei0_isp( void );
0174 extern void _eri1_isp( void );
0175 extern void _rxi1_isp( void );
0176 extern void _txi1_isp( void );
0177 extern void _tei1_isp( void );
0178
0179 /* ADC */
0180 extern void _adi0_isp( void );
0181 extern void _adi1_isp( void );
0182
0183 /* Data Transfer Controller */
0184 extern void _dtci_isp( void );
0185
0186 /* Compare Match Timer */
0187 extern void _cmt0_isp( void );
0188 extern void _cmt1_isp( void );
0189
0190 /* Watchdog Timer */
0191 extern void _wdt_isp( void );
0192
0193 /* DRAM refresh control unit of bus state controller */
0194 extern void _bsc_isp( void );
0195
0196 /* I/O Port */
0197 extern void _oei_isp( void );
0198
0199 /* Parity Control Unit of the Bus State Controllers */
0200 /* extern void _prt_isp( void ); */
0201
0202 #ifdef __cplusplus
0203 }
0204 #endif
0205
0206 #endif