rtems/score/iosh7045.h

0001 /*
0002  *  This include file contains information pertaining to the Hitachi SH
0003  *  processor.
0004  *
0005  *  NOTE: NOT ALL VALUES HAVE BEEN CHECKED !!
0006  *
0007  *  Authors: Ralf Corsepius (corsepiu@faw.uni-ulm.de) and
0008  *           Bernd Becker (becker@faw.uni-ulm.de)
0009  *
0010  *  Based on "iosh7030.h" distributed with Hitachi's EVB's tutorials, which
0011  *  contained no copyright notice.
0012  *
0013  *  COPYRIGHT (c) 1997-1998, FAW Ulm, Germany
0014  *
0015  *  This program is distributed in the hope that it will be useful,
0016  *  but WITHOUT ANY WARRANTY; without even the implied warranty of
0017  *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
0018  *
0019  *
0020  *  COPYRIGHT (c) 1998.
0021  *  On-Line Applications Research Corporation (OAR).
0022  *
0023  *  The license and distribution terms for this file may be
0024  *  found in the file LICENSE in this distribution or at
0025  *  http://www.rtems.org/license/LICENSE.
0026  *
0027  *  Modified to reflect on-chip registers for sh7045 processor, based on
0028  *  "Register.h" distributed with Hitachi's EVB7045F tutorials, and which
0029  *  contained no copyright notice:
0030  *  John M. Mills (jmills@tga.com)
0031  *  TGA Technologies, Inc.
0032  *  100 Pinnacle Way, Suite 140
0033  *  Norcross, GA 30071 U.S.A.
0034  *  August, 1999
0035  *
0036  *  This modified file may be copied and distributed in accordance
0037  *  the above-referenced license. It is provided for critique and
0038  *  developmental purposes without any warranty nor representation
0039  *  by the authors or by TGA Technologies.
0040  */
0041
0042 #ifndef __IOSH7045_H
0043 #define __IOSH7045_H
0044
0045 /*
0046  * After each line is explained whether the access is char short or long.
0047  * The functions read/writeb, w, l, 8, 16, 32 can be found
0048  * in exec/score/cpu/sh/sh_io.h
0049  *
0050  * 8 bit  == char     ( readb, writeb, read8, write8)
0051  * 16 bit == short    ( readw, writew, read16, write16 )
0052  * 32 bit == long     ( readl, writel, read32, write32 )
0053  * JMM: Addresses noted "[char, ]short,word" are per Hitachi _SuperH_RISC_
0054  *      ENGINE_..Hardware_Manual; alignment access-restrictions may apply
0055  */
0056
0057 #define REG_BASE    0xFFFF8000
0058
0059 /* SCI0 Registers */
0060 #define SCI_SMR0   (REG_BASE + 0x01a0) /*char: Serial mode     ch 0 */
0061 #define SCI_BRR0   (REG_BASE + 0x01a1) /*char: Bit rate        ch 0 */
0062 #define SCI_SCR0   (REG_BASE + 0x01a2) /*char: Serial control  ch 0 */
0063 #define SCI_TDR0   (REG_BASE + 0x01a3) /*char: Transmit data   ch 0 */
0064 #define SCI_SSR0   (REG_BASE + 0x01a4) /*char: Serial status   ch 0 */
0065 #define SCI_RDR0   (REG_BASE + 0x01a5) /*char: Receive data    ch 0 */
0066
0067 #define SCI0_SMR   SCI_SMR0
0068
0069 /* SCI1 Registers */
0070 #define SCI_SMR1   (REG_BASE + 0x01b0) /* char: Serial mode     ch 1 */
0071 #define SCI_BRR1   (REG_BASE + 0x01b1) /* char: Bit rate        ch 1 */
0072 #define SCI_SCR1   (REG_BASE + 0x01b2) /* char: Serial control  ch 1 */
0073 #define SCI_TDR1   (REG_BASE + 0x01b3) /* char: Transmit data   ch 1 */
0074 #define SCI_SSR1   (REG_BASE + 0x01b4) /* char: Serial status   ch 1 */
0075 #define SCI_RDR1   (REG_BASE + 0x01b5) /* char: Receive data    ch 1 */
0076
0077 #define SCI1_SMR   SCI_SMR1
0078
0079 /* ADI */
0080 /* High Speed A/D (Excluding A-Mask Part)*/
0081 #define ADDRA      (REG_BASE + 0x03F0) /* short */
0082 #define ADDRB      (REG_BASE + 0x03F2) /* short */
0083 #define ADDRC      (REG_BASE + 0x03F4) /* short */
0084 #define ADDRD      (REG_BASE + 0x03F6) /* short */
0085 #define ADDRE      (REG_BASE + 0x03F8) /* short */
0086 #define ADDRF      (REG_BASE + 0x03FA) /* short */
0087 #define ADDRG      (REG_BASE + 0x03FC) /* short */
0088 #define ADDRH      (REG_BASE + 0x03FE) /* short */
0089 #define ADCSR      (REG_BASE + 0x03E0) /* char  */
0090 #define ADCR       (REG_BASE + 0x03E1) /* char  */
0091
0092 /* Mid-Speed A/D (A-Mask part)*/
0093 #define ADDRA0     (REG_BASE + 0x0400) /* char, short */
0094 #define ADDRA0H    (REG_BASE + 0x0400) /* char, short */
0095 #define ADDRA0L    (REG_BASE + 0x0401) /* char  */
0096 #define ADDRB0     (REG_BASE + 0x0402) /* char, short */
0097 #define ADDRB0H    (REG_BASE + 0x0402) /* char, short */
0098 #define ADDRB0L    (REG_BASE + 0x0403) /* char  */
0099 #define ADDRC0     (REG_BASE + 0x0404) /* char, short */
0100 #define ADDRC0H    (REG_BASE + 0x0404) /* char, short */
0101 #define ADDRC0L    (REG_BASE + 0x0405) /* char  */
0102 #define ADDRD0     (REG_BASE + 0x0406) /* char, short */
0103 #define ADDRD0H    (REG_BASE + 0x0406) /* char, short  */
0104 #define ADDRD0L    (REG_BASE + 0x0407) /* char  */
0105 #define ADCSR0     (REG_BASE + 0x0410) /* char  */
0106 #define ADCR0      (REG_BASE + 0x0412) /* char  */
0107 #define ADDRA1     (REG_BASE + 0x0408) /* char, short */
0108 #define ADDRA1H    (REG_BASE + 0x0408) /* char, short */
0109 #define ADDRA1L    (REG_BASE + 0x0409) /* char  */
0110 #define ADDRB1     (REG_BASE + 0x040A) /* char, short */
0111 #define ADDRB1H    (REG_BASE + 0x040A) /* char, short */
0112 #define ADDRB1L    (REG_BASE + 0x040B) /* char  */
0113 #define ADDRC1     (REG_BASE + 0x040C) /* char, short */
0114 #define ADDRC1H    (REG_BASE + 0x040C) /* char, short */
0115 #define ADDRC1L    (REG_BASE + 0x040D) /* char  */
0116 #define ADDRD1     (REG_BASE + 0x040E) /* char, short */
0117 #define ADDRD1H    (REG_BASE + 0x040E) /* char, short  */
0118 #define ADDRD1L    (REG_BASE + 0x040F) /* char  */
0119 #define ADCSR1     (REG_BASE + 0x0411) /* char  */
0120 #define ADCR1      (REG_BASE + 0x0413) /* char  */
0121
0122 /*MTU SHARED*/
0123 #define MTU_TSTR   (REG_BASE + 0x0240) /* char, short, word  */
0124 #define MTU_TSYR   (REG_BASE + 0x0241) /* char, short, word  */
0125 #define MTU_ICSR   (REG_BASE + 0x03C0) /* input lev. CSR */
0126 #define MTU_OCSR   (REG_BASE + 0x03C0) /* output lev. CSR */
0127
0128 /*MTU CHANNEL 0*/
0129 #define MTU_TCR0   (REG_BASE + 0x0260) /* char, short, word  */
0130 #define MTU_TMDR0  (REG_BASE + 0x0261) /* char, short, word  */
0131 #define MTU_TIORH0 (REG_BASE + 0x0262) /* char, short, word  */
0132 #define MTU_TIORL0 (REG_BASE + 0x0263) /* char, short, word  */
0133 #define MTU_TIER0  (REG_BASE + 0x0264) /* char, short, word  */
0134 #define MTU_TSR0   (REG_BASE + 0x0265) /* char, short, word  */
0135 #define MTU_TCNT0  (REG_BASE + 0x0266) /* short, word */
0136 #define MTU_GR0A   (REG_BASE + 0x0268) /* short, word */
0137 #define MTU_GR0B   (REG_BASE + 0x026A) /* short, word */
0138 #define MTU_GR0C   (REG_BASE + 0x026C) /* short, word */
0139 #define MTU_GR0D   (REG_BASE + 0x026E) /* short, word */
0140
0141 /*MTU CHANNEL 1*/
0142 #define MTU_TCR1   (REG_BASE + 0x0280) /* char, short, word  */
0143 #define MTU_TMDR1  (REG_BASE + 0x0281) /* char, short, word  */
0144 #define MTU_TIOR1  (REG_BASE + 0x0282) /* char, short, word  */
0145 #define MTU_TIER1  (REG_BASE + 0x0284) /* char, short, word  */
0146 #define MTU_TSR1   (REG_BASE + 0x0285) /* char, short, word  */
0147 #define MTU_TCNT1  (REG_BASE + 0x0286) /* short, word */
0148 #define MTU_GR1A   (REG_BASE + 0x0288) /* short, word */
0149 #define MTU_GR1B   (REG_BASE + 0x028A) /* short, word */
0150
0151 /*MTU CHANNEL 2*/
0152 #define MTU_TCR2   (REG_BASE + 0x02A0) /* char, short, word  */
0153 #define MTU_TMDR2  (REG_BASE + 0x02A1) /* char, short, word  */
0154 #define MTU_TIOR2  (REG_BASE + 0x02A2) /* char, short, word  */
0155 #define MTU_TIER2  (REG_BASE + 0x02A4) /* char, short, word  */
0156 #define MTU_TSR2   (REG_BASE + 0x02A5) /* char, short, word  */
0157 #define MTU_TCNT2  (REG_BASE + 0x02A6) /* short, word */
0158 #define MTU_GR2A   (REG_BASE + 0x02A8) /* short, word */
0159 #define MTU_GR2B   (REG_BASE + 0x02AA) /* short, word */
0160
0161 /*MTU CHANNELS 3-4 SHARED*/
0162 #define MTU_TOER   (REG_BASE + 0x020A) /* char, short, word  */
0163 #define MTU_TOCR   (REG_BASE + 0x020B) /* char, short, word  */
0164 #define MTU_TGCR   (REG_BASE + 0x020D) /* char, short, word  */
0165 #define MTU_TCDR   (REG_BASE + 0x0214) /* short, word  */
0166 #define MTU_TDDR   (REG_BASE + 0x0216) /* short, word  */
0167 #define MTU_TCNTS  (REG_BASE + 0x0220) /* short, word  */
0168 #define MTU_TCBR   (REG_BASE + 0x0222) /* short, word  */
0169
0170 /*MTU CHANNEL 3*/
0171 #define MTU_TCR3   (REG_BASE + 0x0200) /* char, short, word  */
0172 #define MTU_TMDR3  (REG_BASE + 0x0202) /* char, short, word  */
0173 #define MTU_TIORH3 (REG_BASE + 0x0204) /* char, short, word  */
0174 #define MTU_TIORL3 (REG_BASE + 0x0205) /* char, short, word  */
0175 #define MTU_TIER3  (REG_BASE + 0x0208) /* char, short, word  */
0176 #define MTU_TSR3   (REG_BASE + 0x022C) /* char, short, word  */
0177 #define MTU_TCNT3  (REG_BASE + 0x0210) /* short, word */
0178 #define MTU_GR3A   (REG_BASE + 0x0218) /* short, word */
0179 #define MTU_GR3B   (REG_BASE + 0x021A) /* short, word */
0180 #define MTU_GR3C   (REG_BASE + 0x0224) /* short, word */
0181 #define MTU_GR3D   (REG_BASE + 0x0226) /* short, word */
0182
0183 /*MTU CHANNEL 4*/
0184 #define MTU_TCR4   (REG_BASE + 0x0201) /* char, short, word  */
0185 #define MTU_TMDR4  (REG_BASE + 0x0203) /* char, short, word  */
0186 #define MTU_TIOR4  (REG_BASE + 0x0206) /* char, short, word  */
0187 #define MTU_TIORH4 (REG_BASE + 0x0206) /* char, short, word  */
0188 #define MTU_TIORL4 (REG_BASE + 0x0207) /* char, short, word  */
0189 #define MTU_TIER4  (REG_BASE + 0x0209) /* char, short, word  */
0190 #define MTU_TSR4   (REG_BASE + 0x022D) /* char, short, word  */
0191 #define MTU_TCNT4  (REG_BASE + 0x0212) /* short, word */
0192 #define MTU_GR4A   (REG_BASE + 0x021C) /* short, word */
0193 #define MTU_GR4B   (REG_BASE + 0x021E) /* short, word */
0194 #define MTU_GR4C   (REG_BASE + 0x0228) /* short, word */
0195 #define MTU_GR4D   (REG_BASE + 0x022A) /* short, word */
0196
0197 /*DMAC CHANNELS 0-3 SHARED*/
0198 #define DMAOR      (REG_BASE + 0x06B0) /* short */
0199
0200 /*DMAC CHANNEL 0*/
0201 #define DMA_SAR0    (REG_BASE + 0x06C0) /* short, word */
0202 #define DMA_DAR0    (REG_BASE + 0x06C4) /* short, word */
0203 #define DMA_DMATCR0 (REG_BASE + 0x06C8) /* short, word */
0204 #define DMA_CHCR0   (REG_BASE + 0x06CC) /* short, word */
0205
0206 /*DMAC CHANNEL 1*/
0207 #define DMA_SAR1    (REG_BASE + 0x06D0) /* short, word */
0208 #define DMA_DAR1    (REG_BASE + 0x06D4) /* short, word */
0209 #define DMA_DMATCR1 (REG_BASE + 0x06D8) /* short, wordt */
0210 #define DMA_CHCR1   (REG_BASE + 0x06DC) /* short, word */
0211
0212 /*DMAC CHANNEL 3*/
0213 #define DMA_SAR3    (REG_BASE + 0x06E0) /* short, word */
0214 #define DMA_DAR3    (REG_BASE + 0x06E4) /* short, word */
0215 #define DMA_DMATCR3 (REG_BASE + 0x06E8) /* short, word */
0216 #define DMA_CHCR3   (REG_BASE + 0x06EC) /* short, word */
0217
0218 /*DMAC CHANNEL 4*/
0219 #define DMA_SAR4    (REG_BASE + 0x06F0) /* short, word */
0220 #define DMA_DAR4    (REG_BASE + 0x06F4) /* short, word */
0221 #define DMA_DMATCR4 (REG_BASE + 0x06F8) /* short, word */
0222 #define DMA_CHCR4   (REG_BASE + 0x06FC) /* short, word */
0223
0224 /*Data Transfer Controller*/
0225 #define DTC_DTEA   (REG_BASE + 0x0700) /* char, short, word */
0226 #define DTC_DTEB   (REG_BASE + 0x0701) /* char, short(?), word(?) */
0227 #define DTC_DTEC   (REG_BASE + 0x0702) /* char, short(?), word(?) */
0228 #define DTC_DTED   (REG_BASE + 0x0703) /* char, short(?), word(?) */
0229 #define DTC_DTEE   (REG_BASE + 0x0704) /* char, short(?), word(?) */
0230 #define DTC_DTCSR  (REG_BASE + 0x0706) /* char, short, word */
0231 #define DTC_DTBR   (REG_BASE + 0x0708) /* short, word */
0232
0233 /*Cache Memory*/
0234 #define CAC_CCR    (REG_BASE + 0x0740) /* char, short, word */
0235
0236 /*INTC*/
0237 #define INTC_IPRA  (REG_BASE + 0x0348) /* char, short, word */
0238 #define INTC_IPRB  (REG_BASE + 0x034A) /* char, short, word */
0239 #define INTC_IPRC  (REG_BASE + 0x034C) /* char, short, word */
0240 #define INTC_IPRD  (REG_BASE + 0x034E) /* char, short, word */
0241 #define INTC_IPRE  (REG_BASE + 0x0350) /* char, short, word */
0242 #define INTC_IPRF  (REG_BASE + 0x0352) /* char, short, word */
0243 #define INTC_IPRG  (REG_BASE + 0x0354) /* char, short, word */
0244 #define INTC_IPRH  (REG_BASE + 0x0356) /* char, short, word */
0245 #define INTC_ICR   (REG_BASE + 0x0358) /* char, short, word */
0246 #define INTC_ISR   (REG_BASE + 0x035A) /* char, short, word */
0247
0248 /*Flash (F-ZTAT)*/
0249 #define FL_FLMCR1  (REG_BASE + 0x0580) /* Fl.Mem.Contr.Reg 1: char */
0250 #define FL_FLMCR2  (REG_BASE + 0x0581) /* Fl.Mem.Contr.Reg 2: char */
0251 #define FL_EBR1    (REG_BASE + 0x0582) /* Fl.Mem.Erase Blk.1: char */
0252 #define FL_EBR2    (REG_BASE + 0x0584) /* Fl.Mem.Erase Blk.2: char */
0253 #define FL_RAMER   (REG_BASE + 0x0628) /* Ram Emul.Reg.- char,short,word */
0254
0255 /*UBC*/
0256 #define UBC_BARH   (REG_BASE + 0x0600) /* char, short, word  */
0257 #define UBC_BARL   (REG_BASE + 0x0602) /* char, short, word  */
0258 #define UBC_BAMRH  (REG_BASE + 0x0604) /* char, short, word  */
0259 #define UBC_BAMRL  (REG_BASE + 0x0606) /* char, short, word  */
0260 #define UBC_BBR    (REG_BASE + 0x0608) /* char, short, word  */
0261 /*BSC*/
0262 #define BSC_BCR1   (REG_BASE + 0x0620) /* short */
0263 #define BSC_BCR2   (REG_BASE + 0x0622) /* short */
0264 #define BSC_WCR1   (REG_BASE + 0x0624) /* short */
0265 #define BSC_WCR2   (REG_BASE + 0x0626) /* short */
0266 #define BSC_DCR    (REG_BASE + 0x062A) /* short */
0267 #define BSC_RTCSR  (REG_BASE + 0x062C) /* short */
0268 #define BSC_RTCNT  (REG_BASE + 0x062E) /* short */
0269 #define BSC_RTCOR  (REG_BASE + 0x0630) /* short */
0270
0271 /*WDT*/
0272 #define WDT_R_TCSR   (REG_BASE + 0x0610) /* rd: char */
0273 #define WDT_R_TCNT   (REG_BASE + 0x0611) /* rd: char */
0274 #define WDT_R_RSTCSR (REG_BASE + 0x0613) /* rd: char */
0275 #define WDT_W_TCSR   (REG_BASE + 0x0610) /* wrt: short */
0276 #define WDT_W_TCNT   (REG_BASE + 0x0610) /* wrt: short */
0277 #define WDT_W_RSTCSR (REG_BASE + 0x0612) /* wrt: short */
0278
0279 /*POWER DOWN STATE*/
0280 #define PDT_SBYCR  (REG_BASE + 0x0614) /* char  */
0281
0282 /* Port I/O  Control Registers */
0283 #define IO_PADRH   (REG_BASE + 0x0380) /* Port A Data Register */
0284 #define IO_PADRL   (REG_BASE + 0x0382) /* Port A Data Register */
0285 #define IO_PBDR    (REG_BASE + 0x0390) /* Port B Data Register */
0286 #define IO_PCDR    (REG_BASE + 0x0392) /* Port C Data Register */
0287 #define IO_PDDRH   (REG_BASE + 0x03A0) /* Port D Data Register */
0288 #define IO_PDDRL   (REG_BASE + 0x03A2) /* Port D Data Register */
0289 #define IO_PEDR    (REG_BASE + 0x03B0) /* Port E Data Register */
0290 #define IO_PFDR    (REG_BASE + 0x03B2) /* Port F Data Register */
0291
0292 /*Pin Function Control Register*/
0293 #define PFC_PAIORH (REG_BASE + 0x0384) /* Port A I/O Reg. H */
0294 #define PFC_PAIORL (REG_BASE + 0x0386) /* Port A I/O Reg. L */
0295 #define PFC_PACRH  (REG_BASE + 0x0388) /* Port A Ctr. Reg. H  */
0296 #define PFC_PACRL1 (REG_BASE + 0x038C) /* Port A Ctr. Reg. L1 */
0297 #define PFC_PACRL2 (REG_BASE + 0x038E) /* Port A Ctr. Reg. L2 */
0298 #define PFC_PBIOR  (REG_BASE + 0x0394) /* Port B I/O Register */
0299 #define PFC_PBCR1  (REG_BASE + 0x0398) /* Port B Ctr. Reg. R1 */
0300 #define PFC_PBCR2  (REG_BASE + 0x039A) /* Port B Ctr. Reg. R2 */
0301 #define PFC_PCIOR  (REG_BASE + 0x0396) /* Port C I/O Register */
0302 #define PFC_PCCR   (REG_BASE + 0x039C) /* Port C Ctr. Reg. */
0303 #define PFC_PDIORH (REG_BASE + 0x03A4) /* Port D I/O Reg. H */
0304 #define PFC_PDIORL (REG_BASE + 0x03A6) /* Port D I/O Reg. L */
0305 #define PFC_PDCRH1 (REG_BASE + 0x03A8) /* Port D Ctr. Reg. H1 */
0306 #define PFC_PDCRH2 (REG_BASE + 0x03AA) /* Port D Ctr. Reg. H2 */
0307 #define PFC_PDCRL  (REG_BASE + 0x03AC) /* Port D Ctr. Reg. L  */
0308 #define PFC_PEIOR  (REG_BASE + 0x03B4) /* Port E I/O Register */
0309 #define PFC_PECR1  (REG_BASE + 0x03B8) /* Port E Ctr. Reg. 1 */
0310 #define PFC_PECR2  (REG_BASE + 0x03BA) /* Port E Ctr. Reg. 2 */
0311 #define PFC_IFCR   (REG_BASE + 0x03C8) /* short */
0312
0313 /*Compare/Match Timer*/
0314 #define CMT_CMSTR  (REG_BASE + 0x3D0) /* Start Reg. char, short, word */
0315 #define CMT_CMCSR0 (REG_BASE + 0x3D2) /* C0 SCR short, word */
0316 #define CMT_CMCNT0 (REG_BASE + 0x3D4) /* C0 Counter char, short, word */
0317 #define CMT_CMCOR0 (REG_BASE + 0x3D6) /* C0 Const.Reg. char, short, word */
0318 #define CMT_CMCSR1 (REG_BASE + 0x3D8) /* C1 SCR short, word */
0319 #define CMT_CMCNT1 (REG_BASE + 0x3DA) /* C1 Counter char, short, word */
0320 #define CMT_CMCOR1 (REG_BASE + 0x3DC) /* C1 Const.Reg. char, short, word */
0321
0322 #endif