gensh2/clock/ckinit.c

0001 /*
0002  *  This file contains the clock driver the Hitachi SH 704X
0003  */
0004
0005 /*
0006  *  Authors: Ralf Corsepius (corsepiu@faw.uni-ulm.de) and
0007  *           Bernd Becker (becker@faw.uni-ulm.de)
0008  *
0009  *  COPYRIGHT (c) 1997-1998, FAW Ulm, Germany
0010  *
0011  *  This program is distributed in the hope that it will be useful,
0012  *  but WITHOUT ANY WARRANTY; without even the implied warranty of
0013  *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
0014  *
0015  *  COPYRIGHT (c) 1998.
0016  *  On-Line Applications Research Corporation (OAR).
0017  *
0018  *      Modified to reflect registers of sh7045 processor:
0019  *      John M. Mills (jmills@tga.com)
0020  *      TGA Technologies, Inc.
0021  *      100 Pinnacle Way, Suite 140
0022  *      Norcross, GA 30071 U.S.A.
0023  *      August, 1999
0024  *
0025  *  This modified file may be copied and distributed in accordance
0026  *  the above-referenced license. It is provided for critique and
0027  *  developmental purposes without any warranty nor representation
0028  *  by the authors or by TGA Technologies.
0029  *
0030  *  The license and distribution terms for this file may be
0031  *  found in the file LICENSE in this distribution or at
0032  *  http://www.rtems.org/license/LICENSE.
0033  */
0034
0035 #include <rtems.h>
0036
0037 #include <stdlib.h>
0038
0039 #include <rtems/clockdrv.h>
0040 #include <rtems/score/sh_io.h>
0041 #include <rtems/score/sh.h>
0042 #include <rtems/score/ispsh7045.h>
0043 #include <rtems/score/iosh7045.h>
0044
0045 static void Clock_exit( void );
0046
0047 extern uint32_t bsp_clicks_per_second;
0048
0049 #define _MTU_COUNTER0_MICROSECOND (Clock_MHZ/16)
0050
0051 #ifndef CLOCKPRIO
0052 #define CLOCKPRIO 10
0053 #endif
0054
0055 #define MTU0_STARTMASK  0xfe
0056 #define MTU0_SYNCMASK   0xfe
0057 #define MTU0_MODEMASK   0xc0
0058 #define MTU0_TCRMASK    0x22 /* bit 7 also used, vs 703x */
0059 #define MTU0_STAT_MASK  0xc0
0060 #define MTU0_IRQMASK    0xfe
0061 #define MTU0_TIERMASK   0x01
0062 #define IPRC_MTU0_MASK  0xff0f
0063 #define MTU0_TIORVAL    0x08
0064
0065 /*
0066  *  The interrupt vector number associated with the clock tick device
0067  *  driver.
0068  */
0069
0070 #define CLOCK_VECTOR MTUA0_ISP_V
0071
0072 /*
0073  *  Clock_driver_ticks is a monotonically increasing counter of the
0074  *  number of clock ticks since the driver was initialized.
0075  */
0076 volatile uint32_t   Clock_driver_ticks;
0077
0078 static rtems_isr Clock_isr( rtems_vector_number vector );
0079 static uint32_t   Clock_MHZ ;
0080
0081 /*
0082  *  Clock_isrs is the number of clock ISRs until the next invocation of
0083  *  the RTEMS clock tick routine.  The clock tick device driver
0084  *  gets an interrupt once a millisecond and counts down until the
0085  *  length of time between the user configured microseconds per tick
0086  *  has passed.
0087  */
0088 uint32_t   Clock_isrs;              /* ISRs until next tick */
0089 static uint32_t   Clock_isrs_const;        /* only calculated once */
0090
0091 /*
0092  *  The previous ISR on this clock tick interrupt vector.
0093  */
0094 rtems_isr_entry  Old_ticker;
0095
0096 /*
0097  *  Isr Handler
0098  */
0099 static rtems_isr Clock_isr(
0100   rtems_vector_number vector
0101 )
0102 {
0103   /*
0104    * bump the number of clock driver ticks since initialization
0105    *
0106
0107    * determine if it is time to announce the passing of tick as configured
0108    * to RTEMS through the rtems_clock_tick directive
0109    *
0110    * perform any timer dependent tasks
0111    */
0112   uint8_t   temp;
0113
0114   /* reset the flags of the status register */
0115   temp = read8( MTU_TSR0) & MTU0_STAT_MASK;
0116   write8( temp, MTU_TSR0);
0117
0118   Clock_driver_ticks++ ;
0119
0120   if( Clock_isrs == 1)
0121     {
0122       rtems_clock_tick();
0123       Clock_isrs = Clock_isrs_const;
0124     }
0125   else
0126     {
0127       Clock_isrs-- ;
0128     }
0129 }
0130
0131 /*
0132  *  Install_clock
0133  *
0134  *  Install a clock tick handler and reprograms the chip.  This
0135  *  is used to initially establish the clock tick.
0136  */
0137 static void Install_clock(
0138   rtems_isr_entry clock_isr
0139 )
0140 {
0141   uint8_t   temp8 = 0;
0142   uint32_t   factor = 1000000;
0143
0144   /*
0145    *  Initialize the clock tick device driver variables
0146    */
0147
0148   Clock_driver_ticks = 0;
0149   Clock_isrs_const = rtems_configuration_get_microseconds_per_tick() / 10000;
0150   Clock_isrs = Clock_isrs_const;
0151
0152   factor /= rtems_configuration_get_microseconds_per_tick(); /* minimalization of integer division error */
0153   Clock_MHZ = bsp_clicks_per_second / factor ;
0154
0155   rtems_interrupt_catch( Clock_isr, CLOCK_VECTOR, &Old_ticker );
0156
0157   /*
0158    *  Hardware specific initialize goes here
0159    */
0160
0161   /* stop Timer 0 */
0162   temp8 = read8( MTU_TSTR) & MTU0_STARTMASK;
0163   write8( temp8, MTU_TSTR);
0164
0165   /* set initial counter value to 0 */
0166   write16( 0, MTU_TCNT0);
0167
0168   /* Timer 0 runs independent */
0169   temp8 = read8( MTU_TSYR) & MTU0_SYNCMASK;
0170   write8( temp8, MTU_TSYR);
0171
0172   /* Timer 0 normal mode */
0173   temp8 = read8( MTU_TMDR0) & MTU0_MODEMASK;
0174   write8( temp8, MTU_TMDR0);
0175
0176   /* TCNT is cleared by GRA ; internal clock /16 */
0177   write8( MTU0_TCRMASK , MTU_TCR0);
0178
0179   /* use GRA without I/O - pins  */
0180   write8( MTU0_TIORVAL, MTU_TIORL0);
0181
0182   /* reset flags of the status register */
0183   temp8 = read8( MTU_TSR0) & MTU0_STAT_MASK;
0184   write8( temp8, MTU_TSR0);
0185
0186   /* Irq if is equal GRA */
0187   temp8 = read8( MTU_TIER0) | MTU0_TIERMASK;
0188   write8( temp8, MTU_TIER0);
0189
0190   /* set interrupt priority */
0191   if( sh_set_irq_priority( CLOCK_VECTOR, CLOCKPRIO ) != RTEMS_SUCCESSFUL)
0192     rtems_fatal_error_occurred( RTEMS_NOT_CONFIGURED);
0193
0194   /* set counter limits */
0195   write16( _MTU_COUNTER0_MICROSECOND, MTU_GR0A);
0196
0197   /* start counter */
0198   temp8 = read8( MTU_TSTR) |~MTU0_STARTMASK;
0199   write8( temp8, MTU_TSTR);
0200
0201   /*
0202    *  Schedule the clock cleanup routine to execute if the application exits.
0203    */
0204   atexit( Clock_exit );
0205 }
0206
0207 /*
0208  *  Clean up before the application exits
0209  */
0210 void Clock_exit( void )
0211 {
0212   uint8_t   temp8 = 0;
0213
0214   /* turn off the timer interrupts */
0215   /* set interrupt priority to 0 */
0216   if( sh_set_irq_priority( CLOCK_VECTOR, 0 ) != RTEMS_SUCCESSFUL)
0217     rtems_fatal_error_occurred( RTEMS_UNSATISFIED);
0218
0219 /*
0220  *   temp16 = read16( MTU_TIER0) & IPRC_MTU0_IRQMASK;
0221  *   write16( temp16, MTU_TIER0);
0222  */
0223
0224   /* stop counter */
0225   temp8 = read8( MTU_TSTR) & MTU0_STARTMASK;
0226   write8( temp8, MTU_TSTR);
0227
0228   /* old vector shall not be installed */
0229 }
0230
0231 void _Clock_Initialize( void )
0232 {
0233   Install_clock( Clock_isr );
0234 }