rtems/score/ispsh7032.h

0001 /*
0002  *  This include file contains information pertaining to the Hitachi SH
0003  *  processor.
0004  *
0005  *  Authors: Ralf Corsepius (corsepiu@faw.uni-ulm.de) and
0006  *           Bernd Becker (becker@faw.uni-ulm.de)
0007  *
0008  *  COPYRIGHT (c) 1997-1998, FAW Ulm, Germany
0009  *
0010  *  This program is distributed in the hope that it will be useful,
0011  *  but WITHOUT ANY WARRANTY; without even the implied warranty of
0012  *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
0013  *
0014  *
0015  *  COPYRIGHT (c) 1998.
0016  *  On-Line Applications Research Corporation (OAR).
0017  *
0018  *  The license and distribution terms for this file may be
0019  *  found in the file LICENSE in this distribution or at
0020  *  http://www.rtems.org/license/LICENSE.
0021  */
0022
0023 #ifndef __CPU_ISPS_H
0024 #define __CPU_ISPS_H
0025
0026 #ifdef __cplusplus
0027 extern "C" {
0028 #endif
0029
0030 extern void __ISR_Handler( uint32_t   vector );
0031
0032
0033 /*
0034  * interrupt vector table offsets
0035  */
0036 #define NMI_ISP_V 11
0037 #define USB_ISP_V 12
0038 #define IRQ0_ISP_V 64
0039 #define IRQ1_ISP_V 65
0040 #define IRQ2_ISP_V 66
0041 #define IRQ3_ISP_V 67
0042 #define IRQ4_ISP_V 68
0043 #define IRQ5_ISP_V 69
0044 #define IRQ6_ISP_V 70
0045 #define IRQ7_ISP_V 71
0046 #define DMA0_ISP_V 72
0047 #define DMA1_ISP_V 74
0048 #define DMA2_ISP_V 76
0049 #define DMA3_ISP_V 78
0050
0051 #define IMIA0_ISP_V 80
0052 #define IMIB0_ISP_V 81
0053 #define OVI0_ISP_V 82
0054
0055 #define IMIA1_ISP_V 84
0056 #define IMIB1_ISP_V 85
0057 #define OVI1_ISP_V 86
0058
0059 #define IMIA2_ISP_V 88
0060 #define IMIB2_ISP_V 89
0061 #define OVI2_ISP_V 90
0062
0063 #define IMIA3_ISP_V 92
0064 #define IMIB3_ISP_V 93
0065 #define OVI3_ISP_V 94
0066
0067 #define IMIA4_ISP_V 96
0068 #define IMIB4_ISP_V 97
0069 #define OVI4_ISP_V 98
0070
0071 #define ERI0_ISP_V 100
0072 #define RXI0_ISP_V 101
0073 #define TXI0_ISP_V 102
0074 #define TEI0_ISP_V 103
0075
0076 #define ERI1_ISP_V 104
0077 #define RXI1_ISP_V 105
0078 #define TXI1_ISP_V 106
0079 #define TEI1_ISP_V 107
0080
0081 #define PRT_ISP_V 108
0082 #define ADU_ISP_V 109
0083 #define WDT_ISP_V 112
0084 #define DREF_ISP_V 113
0085
0086
0087 /* dummy ISP */
0088 extern void _dummy_isp( void );
0089
0090 /* Non Maskable Interrupt */
0091 extern void _nmi_isp( void );
0092
0093 /* User Break Controller */
0094 extern void _usb_isp( void );
0095
0096 /* External interrupts 0-7 */
0097 extern void _irq0_isp( void );
0098 extern void _irq1_isp( void );
0099 extern void _irq2_isp( void );
0100 extern void _irq3_isp( void );
0101 extern void _irq4_isp( void );
0102 extern void _irq5_isp( void );
0103 extern void _irq6_isp( void );
0104 extern void _irq7_isp( void );
0105
0106 /* DMA - Controller */
0107 extern void _dma0_isp( void );
0108 extern void _dma1_isp( void );
0109 extern void _dma2_isp( void );
0110 extern void _dma3_isp( void );
0111
0112 /* Interrupt Timer Unit */
0113 /* Timer 0 */
0114 extern void _imia0_isp( void );
0115 extern void _imib0_isp( void );
0116 extern void _ovi0_isp( void );
0117 /* Timer 1 */
0118 extern void _imia1_isp( void );
0119 extern void _imib1_isp( void );
0120 extern void _ovi1_isp( void );
0121 /* Timer 2 */
0122 extern void _imia2_isp( void );
0123 extern void _imib2_isp( void );
0124 extern void _ovi2_isp( void );
0125 /* Timer 3 */
0126 extern void _imia3_isp( void );
0127 extern void _imib3_isp( void );
0128 extern void _ovi3_isp( void );
0129 /* Timer 4 */
0130 extern void _imia4_isp( void );
0131 extern void _imib4_isp( void );
0132 extern void _ovi4_isp( void );
0133
0134 /* seriell interfaces */
0135 extern void _eri0_isp( void );
0136 extern void _rxi0_isp( void );
0137 extern void _txi0_isp( void );
0138 extern void _tei0_isp( void );
0139 extern void _eri1_isp( void );
0140 extern void _rxi1_isp( void );
0141 extern void _txi1_isp( void );
0142 extern void _tei1_isp( void );
0143
0144 /* Parity Control Unit of the Bus State Controllers */
0145 extern void _prt_isp( void );
0146
0147 /* ADC */
0148 extern void _adu_isp( void );
0149
0150 /* Watchdog Timer */
0151 extern void _wdt_isp( void );
0152
0153 /* DRAM refresh control unit of bus state controller */
0154 extern void _dref_isp( void );
0155
0156 #ifdef __cplusplus
0157 }
0158 #endif
0159
0160 #endif