rtems/score/iosh7032.h

0001 /*
0002  *  This include file contains information pertaining to the Hitachi SH
0003  *  processor.
0004  *
0005  *  NOTE: NOT ALL VALUES HAVE BEEN CHECKED !!
0006  *
0007  *  Authors: Ralf Corsepius (corsepiu@faw.uni-ulm.de) and
0008  *           Bernd Becker (becker@faw.uni-ulm.de)
0009  *
0010  *  Based on "iosh7030.h" distributed with Hitachi's EVB's tutorials, which
0011  *  contained no copyright notice.
0012  *
0013  *  COPYRIGHT (c) 1997-1998, FAW Ulm, Germany
0014  *
0015  *  This program is distributed in the hope that it will be useful,
0016  *  but WITHOUT ANY WARRANTY; without even the implied warranty of
0017  *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
0018  *
0019  *
0020  *  COPYRIGHT (c) 1998.
0021  *  On-Line Applications Research Corporation (OAR).
0022  *
0023  *  The license and distribution terms for this file may be
0024  *  found in the file LICENSE in this distribution or at
0025  *  http://www.rtems.org/license/LICENSE.
0026  */
0027
0028 #ifndef __IOSH7030_H
0029 #define __IOSH7030_H
0030
0031 /*
0032  * After each line is explained whether the access is char short or long.
0033  * The functions read/writeb, w, l, 8, 16, 32 can be found
0034  * in exec/score/cpu/sh/sh_io.h
0035  *
0036  * 8 bit  == char     ( readb, writeb, read8, write8)
0037  * 16 bit == short    ( readw, writew, read16, write16 )
0038  * 32 bit == long     ( readl, writel, read32, write32 )
0039  */
0040
0041 #define SCI0_SMR    0x05fffec0 /* char  */
0042 #define SCI0_BRR    0x05fffec1 /* char  */
0043 #define SCI0_SCR    0x05fffec2 /* char  */
0044 #define SCI0_TDR    0x05fffec3 /* char  */
0045 #define SCI0_SSR    0x05fffec4 /* char  */
0046 #define SCI0_RDR    0x05fffec5 /* char  */
0047
0048 #define SCI1_SMR    0x05fffec8 /* char  */
0049 #define SCI1_BRR    0x05fffec9 /* char  */
0050 #define SCI1_SCR    0x05fffeca /* char  */
0051 #define SCI1_TDR    0x05fffecb /* char  */
0052 #define SCI1_SSR    0x05fffecc /* char  */
0053 #define SCI1_RDR    0x05fffecd /* char  */
0054
0055
0056 #define ADDRAH      0x05fffee0 /* char  */
0057 #define ADDRAL      0x05fffee1 /* char  */
0058 #define ADDRBH      0x05fffee2 /* char  */
0059 #define ADDRBL      0x05fffee3 /* char  */
0060 #define ADDRCH      0x05fffee4 /* char  */
0061 #define ADDRCL      0x05fffee5 /* char  */
0062 #define ADDRDH      0x05fffee6 /* char  */
0063 #define ADDRDL      0x05fffee7 /* char  */
0064 #define AD_DRA      0x05fffee0 /* short */
0065 #define AD_DRB      0x05fffee2 /* short */
0066 #define AD_DRC      0x05fffee4 /* short */
0067 #define AD_DRD      0x05fffee6 /* short */
0068 #define ADCSR       0x05fffee8 /* char  */
0069 #define ADCR        0x05fffee9 /* char  */
0070
0071 /*ITU SHARED*/
0072 #define ITU_TSTR    0x05ffff00 /* char  */
0073 #define ITU_TSNC    0x05ffff01 /* char  */
0074 #define ITU_TMDR    0x05ffff02 /* char  */
0075 #define ITU_TFCR    0x05ffff03 /* char  */
0076
0077 /*ITU CHANNEL 0*/
0078 #define ITU_TCR0    0x05ffff04 /* char  */
0079 #define ITU_TIOR0   0x05ffff05 /* char  */
0080 #define ITU_TIER0   0x05ffff06 /* char  */
0081 #define ITU_TSR0    0x05ffff07 /* char  */
0082 #define ITU_TCNT0   0x05ffff08 /* short */
0083 #define ITU_GRA0    0x05ffff0a /* short */
0084 #define ITU_GRB0    0x05ffff0c /* short */
0085
0086  /*ITU CHANNEL 1*/
0087 #define ITU_TCR1    0x05ffff0E /* char  */
0088 #define ITU_TIOR1   0x05ffff0F /* char  */
0089 #define ITU_TIER1   0x05ffff10 /* char  */
0090 #define ITU_TSR1    0x05ffff11 /* char  */
0091 #define ITU_TCNT1   0x05ffff12 /* short */
0092 #define ITU_GRA1    0x05ffff14 /* short */
0093 #define ITU_GRB1    0x05ffff16 /* short */
0094
0095
0096  /*ITU CHANNEL 2*/
0097 #define ITU_TCR2    0x05ffff18 /* char  */
0098 #define ITU_TIOR2   0x05ffff19 /* char  */
0099 #define ITU_TIER2   0x05ffff1A /* char  */
0100 #define ITU_TSR2    0x05ffff1B /* char  */
0101 #define ITU_TCNT2   0x05ffff1C /* short */
0102 #define ITU_GRA2    0x05ffff1E /* short */
0103 #define ITU_GRB2    0x05ffff20 /* short */
0104
0105  /*ITU CHANNEL 3*/
0106 #define ITU_TCR3    0x05ffff22 /* char  */
0107 #define ITU_TIOR3   0x05ffff23 /* char  */
0108 #define ITU_TIER3   0x05ffff24 /* char  */
0109 #define ITU_TSR3    0x05ffff25 /* char  */
0110 #define ITU_TCNT3   0x05ffff26 /* short */
0111 #define ITU_GRA3    0x05ffff28 /* short */
0112 #define ITU_GRB3    0x05ffff2A /* short */
0113 #define ITU_BRA3    0x05ffff2C /* short */
0114 #define ITU_BRB3    0x05ffff2E /* short */
0115
0116  /*ITU CHANNELS 0-4 SHARED*/
0117 #define ITU_TOCR    0x05ffff31 /* char  */
0118
0119  /*ITU CHANNEL 4*/
0120 #define ITU_TCR4    0x05ffff32 /* char  */
0121 #define ITU_TIOR4   0x05ffff33 /* char  */
0122 #define ITU_TIER4   0x05ffff34 /* char  */
0123 #define ITU_TSR4    0x05ffff35 /* char  */
0124 #define ITU_TCNT4   0x05ffff36 /* short */
0125 #define ITU_GRA4    0x05ffff38 /* short */
0126 #define ITU_GRB4    0x05ffff3A /* short */
0127 #define ITU_BRA4    0x05ffff3C /* short */
0128 #define ITU_BRB4    0x05ffff3E /* short */
0129
0130  /*DMAC CHANNELS 0-3 SHARED*/
0131 #define DMAOR           0x05ffff48 /* short */
0132
0133  /*DMAC CHANNEL 0*/
0134 #define DMA_SAR0        0x05ffff40 /* long  */
0135 #define DMA_DAR0        0x05ffff44 /* long  */
0136 #define DMA_TCR0        0x05ffff4a /* short */
0137 #define DMA_CHCR0       0x05ffff4e /* short */
0138
0139  /*DMAC CHANNEL 1*/
0140 #define DMA_SAR1        0x05ffff50 /* long  */
0141 #define DMA_DAR1        0x05ffff54 /* long  */
0142 #define DMA_TCR1        0x05fffF5a /* short */
0143 #define DMA_CHCR1       0x05ffff5e /* short */
0144
0145  /*DMAC CHANNEL 3*/
0146 #define DMA_SAR3        0x05ffff60 /* long  */
0147 #define DMA_DAR3        0x05ffff64 /* long  */
0148 #define DMA_TCR3        0x05fffF6a /* short */
0149 #define DMA_CHCR3       0x05ffff6e /* short */
0150
0151 /*DMAC CHANNEL 4*/
0152 #define DMA_SAR4        0x05ffff70 /* long  */
0153 #define DMA_DAR4        0x05ffff74 /* long  */
0154 #define DMA_TCR4        0x05fffF7a /* short */
0155 #define DMA_CHCR4       0x05ffff7e /* short */
0156
0157 /*INTC*/
0158 #define INTC_IPRA   0x05ffff84 /* short */
0159 #define INTC_IPRB   0x05ffff86 /* short */
0160 #define INTC_IPRC   0x05ffff88 /* short */
0161 #define INTC_IPRD   0x05ffff8A /* short */
0162 #define INTC_IPRE   0x05ffff8C /* short */
0163 #define INTC_ICR    0x05ffff8E /* short */
0164
0165 /*UBC*/
0166 #define UBC_BARH    0x05ffff90 /* short */
0167 #define UBC_BARL    0x05ffff92 /* short */
0168 #define UBC_BAMRH   0x05ffff94 /* short */
0169 #define UBC_BAMRL   0x05ffff96 /* short */
0170 #define UBC_BBR     0x05ffff98 /* short */
0171
0172 /*BSC*/
0173 #define BSC_BCR     0x05ffffA0 /* short */
0174 #define BSC_WCR1    0x05ffffA2 /* short */
0175 #define BSC_WCR2    0x05ffffA4 /* short */
0176 #define BSC_WCR3    0x05ffffA6 /* short */
0177 #define BSC_DCR     0x05ffffA8 /* short */
0178 #define BSC_PCR     0x05ffffAA /* short */
0179 #define BSC_RCR     0x05ffffAC /* short */
0180 #define BSC_RTCSR   0x05ffffAE /* short */
0181 #define BSC_RTCNT   0x05ffffB0 /* short */
0182 #define BSC_RTCOR   0x05ffffB2 /* short */
0183
0184 /*WDT*/
0185 #define WDT_TCSR    0x05ffffB8 /* char  */
0186 #define WDT_TCNT    0x05ffffB9 /* char  */
0187 #define WDT_RSTCSR  0x05ffffBB /* char  */
0188
0189 /*POWER DOWN STATE*/
0190 #define PDT_SBYCR   0x05ffffBC /* char  */
0191
0192 /*PORT A*/
0193 #define PADR        0x05ffffC0 /* short */
0194
0195 /*PORT B*/
0196 #define PBDR        0x05ffffC2 /* short */
0197
0198  /*PORT C*/
0199 #define PCDR        0x05ffffD0 /* short */
0200
0201 /*PFC*/
0202 #define PFC_PAIOR   0x05ffffC4 /* short */
0203 #define PFC_PBIOR   0x05ffffC6 /* short */
0204 #define PFC_PACR1   0x05ffffC8 /* short */
0205 #define PFC_PACR2   0x05ffffCA /* short */
0206 #define PFC_PBCR1   0x05ffffCC /* short */
0207 #define PFC_PBCR2   0x05ffffCE /* short */
0208 #define PFC_CASCR   0x05ffffEE /* short */
0209
0210 /*TPC*/
0211 #define TPC_TPMR    0x05ffffF0 /* short */
0212 #define TPC_TPCR    0x05ffffF1 /* short */
0213 #define TPC_NDERH   0x05ffffF2 /* short */
0214 #define TPC_NDERL   0x05ffffF3 /* short */
0215 #define TPC_NDRB    0x05ffffF4 /* char  */
0216 #define TPC_NDRA    0x05ffffF5 /* char  */
0217 #define TPC_NDRB1   0x05ffffF6 /* char  */
0218 #define TPC_NDRA1   0x05ffffF7 /* char  */
0219
0220 #endif