gensh1/clock/ckinit.c

0001 /*
0002  *  This file contains the clock driver the Hitachi SH 703X
0003  */
0004
0005 /*
0006  *  Authors: Ralf Corsepius (corsepiu@faw.uni-ulm.de) and
0007  *           Bernd Becker (becker@faw.uni-ulm.de)
0008  *
0009  *  COPYRIGHT (c) 1997-1998, FAW Ulm, Germany
0010  *
0011  *  This program is distributed in the hope that it will be useful,
0012  *  but WITHOUT ANY WARRANTY; without even the implied warranty of
0013  *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
0014  *
0015  *  COPYRIGHT (c) 1998.
0016  *  On-Line Applications Research Corporation (OAR).
0017  *
0018  *  The license and distribution terms for this file may be
0019  *  found in the file LICENSE in this distribution or at
0020  *  http://www.rtems.org/license/LICENSE.
0021  */
0022
0023 #include <rtems.h>
0024
0025 #include <stdlib.h>
0026
0027 #include <rtems/clockdrv.h>
0028 #include <rtems/score/sh_io.h>
0029 #include <rtems/score/sh.h>
0030 #include <rtems/score/ispsh7032.h>
0031 #include <rtems/score/iosh7032.h>
0032
0033 extern uint32_t bsp_clicks_per_second;
0034
0035 #ifndef CLOCKPRIO
0036 #define CLOCKPRIO 10
0037 #endif
0038
0039 #define I_CLK_PHI_1 0
0040 #define I_CLK_PHI_2 1
0041 #define I_CLK_PHI_4 2
0042 #define I_CLK_PHI_8 3
0043
0044 /*
0045  * Set I_CLK_PHI to one of the I_CLK_PHI_X values from above to choose
0046  * a PHI/X clock rate.
0047  */
0048
0049 #define I_CLK_PHI   I_CLK_PHI_4
0050 #define CLOCK_SCALE (1<<I_CLK_PHI)
0051
0052 #define ITU0_STARTMASK  0xfe
0053 #define ITU0_SYNCMASK   0xfe
0054 #define ITU0_MODEMASK   0xfe
0055 #define ITU0_TCRMASK    (0x20 | I_CLK_PHI)
0056 #define ITU_STAT_MASK   0xf8
0057 #define ITU0_IRQMASK    0xfe
0058 #define ITU0_TIERMASK   0x01
0059 #define IPRC_ITU0_MASK  0xff0f
0060 #define ITU0_TIORVAL    0x08
0061
0062 /*
0063  * clicks_per_tick := clicks_per_sec * usec_per_tick
0064  *
0065  * This is a very expensive function ;-)
0066  *
0067  * Below are two variants:
0068  * 1. A variant applying integer arithmetics, only.
0069  * 2. A variant applying floating point arithmetics
0070  *
0071  * The floating point variant pulls in the fmath routines when linking,
0072  * resulting in slightly larger executables for applications that do not
0073  * apply fmath otherwise. However, the imath variant is significantly slower
0074  * than the fmath variant and more complex.
0075  *
0076  * Assuming that most applications will not use fmath, but are critical
0077  * in memory size constraints, we apply the integer variant.
0078  *
0079  * To the sake of simplicity, we might abandon one of both variants in
0080  * future.
0081  */
0082 static unsigned int sh_clicks_per_tick(
0083   unsigned int clicks_per_sec,
0084   unsigned int usec_per_tick
0085 )
0086 {
0087 #if 1
0088   unsigned int clicks_per_tick = 0 ;
0089
0090   unsigned int b = clicks_per_sec ;
0091   unsigned int c = 1000000 ;
0092   unsigned int d = 1 ;
0093   unsigned int a = ( ( b / c ) * usec_per_tick ) / d;
0094
0095   clicks_per_tick += a ;
0096
0097   while ( ( b %= c ) > 0 )
0098   {
0099     c /= 10 ;
0100     d *= 10 ;
0101     a = ( ( b / c ) * usec_per_tick ) / d ;
0102     clicks_per_tick += a ;
0103   }
0104   return clicks_per_tick ;
0105 #else
0106   double fclicks_per_tick =
0107     ((double) clicks_per_sec * (double) usec_per_tick) / 1000000.0 ;
0108   return (uint32_t) fclicks_per_tick ;
0109 #endif
0110 }
0111
0112 /*
0113  *  The interrupt vector number associated with the clock tick device
0114  *  driver.
0115  */
0116
0117 #define CLOCK_VECTOR IMIA0_ISP_V
0118
0119 /*
0120  *  Clock_driver_ticks is a monotonically increasing counter of the
0121  *  number of clock ticks since the driver was initialized.
0122  */
0123
0124 volatile uint32_t   Clock_driver_ticks;
0125
0126 static void Clock_exit( void );
0127 static rtems_isr Clock_isr( rtems_vector_number vector );
0128
0129 /*
0130  *  Clock_isrs is the number of clock ISRs until the next invocation of
0131  *  the RTEMS clock tick routine.  The clock tick device driver
0132  *  gets an interrupt once a millisecond and counts down until the
0133  *  length of time between the user configured microseconds per tick
0134  *  has passed.
0135  */
0136
0137 uint32_t   Clock_isrs;              /* ISRs until next tick */
0138 static uint32_t   Clock_isrs_const;        /* only calculated once */
0139
0140 /*
0141  *  The previous ISR on this clock tick interrupt vector.
0142  */
0143 rtems_isr_entry  Old_ticker;
0144
0145 /*
0146  *  Isr Handler
0147  */
0148 static rtems_isr Clock_isr(
0149   rtems_vector_number vector
0150 )
0151 {
0152   /*
0153    * bump the number of clock driver ticks since initialization
0154    *
0155    * determine if it is time to announce the passing of tick as configured
0156    * to RTEMS through the rtems_clock_tick directive
0157    *
0158    * perform any timer dependent tasks
0159    */
0160   uint8_t   temp;
0161
0162   /* reset the flags of the status register */
0163   temp = read8( ITU_TSR0) & ITU_STAT_MASK;
0164   write8( temp, ITU_TSR0);
0165
0166   Clock_driver_ticks++ ;
0167
0168   if( Clock_isrs == 1)
0169     {
0170       rtems_clock_tick();
0171       Clock_isrs = Clock_isrs_const;
0172     }
0173   else
0174     {
0175       Clock_isrs-- ;
0176     }
0177 }
0178
0179 /*
0180  *  Install_clock
0181  *
0182  *  Install a clock tick handler and reprograms the chip.  This
0183  *  is used to initially establish the clock tick.
0184  */
0185 static void Install_clock(
0186   rtems_isr_entry clock_isr
0187 )
0188 {
0189   uint8_t   temp8 = 0;
0190   uint32_t   microseconds_per_tick;
0191   uint32_t   cclicks_per_tick;
0192   uint16_t   Clock_limit;
0193
0194   /*
0195    *  Initialize the clock tick device driver variables
0196    */
0197
0198   Clock_driver_ticks = 0;
0199
0200   if ( rtems_configuration_get_microseconds_per_tick() != 0 )
0201     microseconds_per_tick = rtems_configuration_get_microseconds_per_tick() ;
0202   else
0203     microseconds_per_tick = 10000 ; /* 10000 us */
0204
0205   /* clock clicks per tick */
0206   cclicks_per_tick = sh_clicks_per_tick(
0207      bsp_clicks_per_second / CLOCK_SCALE, microseconds_per_tick );
0208
0209   Clock_isrs_const = cclicks_per_tick >> 16 ;
0210   if ( ( cclicks_per_tick | 0xffff ) > 0 )
0211     Clock_isrs_const++ ;
0212   Clock_limit = cclicks_per_tick / Clock_isrs_const ;
0213   Clock_isrs = Clock_isrs_const;
0214
0215   rtems_interrupt_catch( Clock_isr, CLOCK_VECTOR, &Old_ticker );
0216   /*
0217    *  Hardware specific initialize goes here
0218    */
0219
0220   /* stop Timer 0 */
0221   temp8 = read8( ITU_TSTR) & ITU0_STARTMASK;
0222   write8( temp8, ITU_TSTR);
0223
0224   /* set initial counter value to 0 */
0225   write16( 0, ITU_TCNT0);
0226
0227   /* Timer 0 runs independent */
0228   temp8 = read8( ITU_TSNC) & ITU0_SYNCMASK;
0229   write8( temp8, ITU_TSNC);
0230
0231   /* Timer 0 normal mode */
0232   temp8 = read8( ITU_TMDR) & ITU0_MODEMASK;
0233   write8( temp8, ITU_TMDR);
0234
0235   /* TCNT is cleared by GRA ; internal clock /4 */
0236   write8( ITU0_TCRMASK , ITU_TCR0);
0237
0238   /* use GRA without I/O - pins  */
0239   write8( ITU0_TIORVAL, ITU_TIOR0);
0240
0241   /* reset flags of the status register */
0242   temp8 = read8( ITU_TSR0) & ITU_STAT_MASK;
0243   write8( temp8, ITU_TSR0);
0244
0245   /* Irq if is equal GRA */
0246   temp8 = read8( ITU_TIER0) | ITU0_TIERMASK;
0247   write8( temp8, ITU_TIER0);
0248
0249   /* set interrupt priority */
0250   if( sh_set_irq_priority( CLOCK_VECTOR, CLOCKPRIO ) != RTEMS_SUCCESSFUL)
0251     rtems_fatal_error_occurred( RTEMS_NOT_CONFIGURED);
0252
0253   /* set counter limits */
0254   write16( Clock_limit, ITU_GRA0);
0255
0256   /* start counter */
0257   temp8 = read8( ITU_TSTR) |~ITU0_STARTMASK;
0258   write8( temp8, ITU_TSTR);
0259
0260   /*
0261    *  Schedule the clock cleanup routine to execute if the application exits.
0262    */
0263
0264   atexit( Clock_exit );
0265 }
0266
0267 /*
0268  *  Clean up before the application exits
0269  */
0270 void Clock_exit( void )
0271 {
0272   uint8_t   temp8 = 0;
0273
0274   /* turn off the timer interrupts */
0275   /* set interrupt priority to 0 */
0276   if( sh_set_irq_priority( CLOCK_VECTOR, 0 ) != RTEMS_SUCCESSFUL)
0277     rtems_fatal_error_occurred( RTEMS_UNSATISFIED);
0278
0279 /*
0280  *   temp16 = read16( ITU_TIER0) & IPRC_ITU0_IRQMASK;
0281  *   write16( temp16, ITU_TIER0);
0282  */
0283
0284   /* stop counter */
0285   temp8 = read8( ITU_TSTR) & ITU0_STARTMASK;
0286   write8( temp8, ITU_TSTR);
0287
0288   /* old vector shall not be installed */
0289 }
0290
0291 void _Clock_Initialize( void )
0292 {
0293   Install_clock( Clock_isr );
0294 }