shared/start/start.S

0001 /*
0002  * Copyright (c) 2018 embedded brains GmbH & Co. KG
0003
0004  * Copyright (c) 2015 University of York.
0005  * Hesham Almatary <hesham@alumni.york.ac.uk>
0006  *
0007  * Copyright (c) 2013, The Regents of the University of California (Regents).
0008  * All Rights Reserved.
0009  *
0010  * Redistribution and use in source and binary forms, with or without
0011  * modification, are permitted provided that the following conditions
0012  * are met:
0013  * 1. Redistributions of source code must retain the above copyright
0014  *    notice, this list of conditions and the following disclaimer.
0015  * 2. Redistributions in binary form must reproduce the above copyright
0016  *    notice, this list of conditions and the following disclaimer in the
0017  *    documentation and/or other materials provided with the distribution.
0018  *
0019  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
0020  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
0021  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
0022  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
0023  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
0024  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
0025  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
0026  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
0027  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
0028  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
0029  * SUCH DAMAGE.
0030  */
0031
0032 #include <rtems/asm.h>
0033 #include <rtems/score/percpu.h>
0034 #include <rtems/score/riscv-utility.h>
0035 #include <bsp/linker-symbols.h>
0036 #include <bspopts.h>
0037
0038 PUBLIC(_start)
0039
0040     .section    .bsp_start_text, "wax", @progbits
0041     .align  2
0042     .option arch, +zicsr
0043     .option norelax
0044
0045 TYPE_FUNC(_start)
0046 SYM(_start):
0047     /* Load global pointer */
0048     .option push
0049     .option norelax
0050     LADDR   gp, __global_pointer$
0051     .option pop
0052
0053     /* Init FPU */
0054 #ifdef __riscv_flen
0055     li  t0, MSTATUS_FS
0056     csrs    mstatus, t0
0057     csrw    fcsr, zero
0058 #endif
0059
0060     /* Set exception handler */
0061     LADDR   t0, _RISCV_Exception_handler
0062     csrw    mtvec, t0
0063
0064     /* Load stack pointer and branch to secondary processor start if necessary */
0065 #ifdef RTEMS_SMP
0066     LADDR   sp, _ISR_Stack_area_begin
0067     LADDR   t2, _ISR_Stack_size
0068     csrr    s0, mhartid
0069     li  t3, RISCV_BOOT_HARTID
0070     sub s0, s0, t3
0071
0072     /*
0073      * Check that this is a configured processor.  If not, then there is
0074      * not much that can be done since we do not have a stack available for
0075      * this processor.  Just loop forever in this case.
0076      */
0077     LREG    t3, _SMP_Processor_configured_maximum
0078     bgeu    s0, t3, .Lwfi
0079
0080     LADDR   t0, _Per_CPU_Information
0081     slli    t1, s0, PER_CPU_CONTROL_SIZE_LOG2
0082     add s1, t0, t1
0083     csrw    mscratch, s1
0084     bnez    s0, .Lstart_on_secondary_processor
0085     add sp, sp, t2
0086 #else
0087     LADDR   sp, _ISR_Stack_area_end
0088 #endif
0089
0090 #ifdef BSP_START_COPY_FDT_FROM_U_BOOT
0091     mv  a0, a1
0092     call    bsp_fdt_copy
0093 #endif
0094
0095     /* Clear .bss */
0096     LADDR   a0, bsp_section_bss_begin
0097     li  a1, 0
0098     LADDR   a2, bsp_section_bss_size
0099     call    memset
0100
0101 #ifdef RTEMS_SMP
0102     /* Give go to secondary processors */
0103     LADDR   t0, .Lsecondary_processor_go
0104     fence   iorw,ow
0105     amoswap.w   zero, zero, 0(t0)
0106 #endif
0107
0108     li  a0, 0
0109     tail    boot_card
0110
0111 #ifdef RTEMS_SMP
0112 .Lwfi:
0113     wfi
0114     j   .Lwfi
0115
0116 .Lstart_on_secondary_processor:
0117
0118     /* Adjust stack pointer */
0119 #ifdef __riscv_mul
0120     addi    t0, s0, 1
0121     mul t2, t2, t0
0122 #else
0123     mv  t0, s0
0124     mv  t3, t2
0125
0126 .Ladd_more:
0127
0128     add t2, t2, t3
0129     addi    t0, t0, -1
0130     bnez    t0, .Ladd_more
0131 #endif
0132     add sp, sp, t2
0133
0134     /* Wait for go issued by the boot processor (mhartid == 0) */
0135     LADDR   t0, .Lsecondary_processor_go
0136
0137 .Lwait_for_go_again:
0138
0139     lw  t1, 0(t0)
0140     fence   iorw, iorw
0141     bnez    t1, .Lwait_for_go_again
0142
0143     mv  a0, s1
0144     call    bsp_start_on_secondary_processor
0145
0146     .section    .bsp_start_data, "aw"
0147
0148     .type   .Lsecondary_processor_go, @object
0149
0150 #if __riscv_xlen == 32
0151     .size   .Lsecondary_processor_go, 4
0152     .align  2
0153 #elif __riscv_xlen == 64
0154     .size   .Lsecondary_processor_go, 8
0155     .align  3
0156 #endif
0157
0158 .Lsecondary_processor_go:
0159
0160     /*
0161      * These are ebreak instructions, just in case we end up here executing
0162      * code.
0163      */
0164     .word   0x00100073
0165 #if __riscv_xlen == 64
0166     .word   0x00100073
0167 #endif
0168
0169 #endif /* RTEMS_SMP */