Back to home page

LXR

 
 

    


File indexing completed on 2025-05-11 08:24:00

0001 /* SPDX-License-Identifier: BSD-2-Clause */
0002 
0003 /*
0004  * Copyright (c) 2018 embedded brains GmbH & Co. KG
0005  *
0006  * Redistribution and use in source and binary forms, with or without
0007  * modification, are permitted provided that the following conditions
0008  * are met:
0009  * 1. Redistributions of source code must retain the above copyright
0010  *    notice, this list of conditions and the following disclaimer.
0011  * 2. Redistributions in binary form must reproduce the above copyright
0012  *    notice, this list of conditions and the following disclaimer in the
0013  *    documentation and/or other materials provided with the distribution.
0014  *
0015  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
0016  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
0017  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
0018  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
0019  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
0020  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
0021  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
0022  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
0023  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
0024  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
0025  * SUCH DAMAGE.
0026  */
0027 
0028 #ifndef BSP_RISCV_H
0029 #define BSP_RISCV_H
0030 
0031 #include <bsp.h>
0032 
0033 #include <rtems/score/cpuimpl.h>
0034 
0035 #ifdef __cplusplus
0036 extern "C" {
0037 #endif
0038 
0039 extern volatile RISCV_CLINT_regs *riscv_clint;
0040 
0041 void *riscv_fdt_get_address(const void *fdt, int node);
0042 
0043 uint32_t riscv_get_core_frequency(void);
0044 
0045 #ifdef RTEMS_SMP
0046 extern uint32_t riscv_hart_count;
0047 #else
0048 #define riscv_hart_count 1
0049 #endif
0050 
0051 uint32_t riscv_get_hart_index_by_phandle(uint32_t phandle);
0052 
0053 #ifdef __cplusplus
0054 }
0055 #endif
0056 
0057 #endif /* BSP_RISCV_H */