include/bsp/irq.h

0001 /* SPDX-License-Identifier: BSD-2-Clause */
0002
0003 /**
0004  * @file
0005  *
0006  * @ingroup RISCV_IRQ
0007  *
0008  * @brief Interrupt definitions.
0009  */
0010
0011 /*
0012  * Copyright (c) 2018 embedded brains GmbH & Co. KG
0013  *
0014  * Copyright (c) 2015 University of York.
0015  * Hesham Almatary <hesham@alumni.york.ac.uk>
0016  *
0017  * Redistribution and use in source and binary forms, with or without
0018  * modification, are permitted provided that the following conditions
0019  * are met:
0020  * 1. Redistributions of source code must retain the above copyright
0021  *    notice, this list of conditions and the following disclaimer.
0022  * 2. Redistributions in binary form must reproduce the above copyright
0023  *    notice, this list of conditions and the following disclaimer in the
0024  *    documentation and/or other materials provided with the distribution.
0025  *
0026  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
0027  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
0028  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
0029  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
0030  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
0031  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
0032  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
0033  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
0034  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
0035  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
0036  * SUCH DAMAGE.
0037  */
0038
0039 #ifndef LIBBSP_GENERIC_RISCV_IRQ_H
0040 #define LIBBSP_GENERIC_RISCV_IRQ_H
0041
0042 #ifndef ASM
0043
0044 #include <bsp.h>
0045
0046 #define RISCV_INTERRUPT_VECTOR_SOFTWARE 0
0047
0048 #define RISCV_INTERRUPT_VECTOR_TIMER 1
0049
0050 #define RISCV_INTERRUPT_VECTOR_EXTERNAL(x) ((x) + 2)
0051
0052 #define RISCV_INTERRUPT_VECTOR_IS_EXTERNAL(x) ((x) >= 2)
0053
0054 #define RISCV_INTERRUPT_VECTOR_EXTERNAL_TO_INDEX(x) ((x) - 2)
0055
0056 #define BSP_INTERRUPT_VECTOR_COUNT RISCV_INTERRUPT_VECTOR_EXTERNAL(RISCV_MAXIMUM_EXTERNAL_INTERRUPTS)
0057
0058 #define BSP_INTERRUPT_CUSTOM_VALID_VECTOR
0059
0060 #endif /* ASM */
0061
0062 #endif /* LIBBSP_GENERIC_RISCV_IRQ_H */