niosv/include/altera_avalon_epcq_regs.h

0001 /* SPDX-License-Identifier: BSD-2-Clause */
0002
0003 /*
0004  *
0005  * Copyright (C) 2024 Kevin Kirspel
0006  *
0007  * Redistribution and use in source and binary forms, with or without
0008  * modification, are permitted provided that the following conditions
0009  * are met:
0010  * 1. Redistributions of source code must retain the above copyright
0011  *    notice, this list of conditions and the following disclaimer.
0012  * 2. Redistributions in binary form must reproduce the above copyright
0013  *    notice, this list of conditions and the following disclaimer in the
0014  *    documentation and/or other materials provided with the distribution.
0015  *
0016  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
0017  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
0018  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
0019  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
0020  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
0021  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
0022  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
0023  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
0024  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
0025  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
0026  * SUCH DAMAGE.
0027  */
0028
0029 #ifndef _ALTERA_AVALON_EPCQ_REGS_H
0030 #define _ALTERA_AVALON_EPCQ_REGS_H
0031
0032 #include <stdbool.h>
0033 #include <bsp_system.h>
0034
0035 /*
0036  * EPCQ_RD_STATUS register description macros
0037  */
0038
0039 /** Write in progress bit */
0040 #define ALTERA_EPCQ_CONTROLLER2_STATUS_WIP_MASK                  (0x00000001)
0041 #define ALTERA_EPCQ_CONTROLLER2_STATUS_WIP_AVAILABLE             (0x00000000)
0042 #define ALTERA_EPCQ_CONTROLLER2_STATUS_WIP_BUSY                  (0x00000001)
0043 /** When to time out a poll of the write in progress bit */
0044 /* 0.7 sec time out */
0045 #define ALTERA_EPCQ_CONTROLLER2_1US_TIMEOUT_VALUE                700000
0046
0047 /*
0048  * EPCQ_RD_SID register description macros
0049  *
0050  * Specific device values obtained from Table 14 of:
0051  * "Serial Configuration (EPCS) Devices Datasheet"
0052  */
0053 #define ALTERA_EPCQ_CONTROLLER2_SID_MASK                         (0x000000FF)
0054 #define ALTERA_EPCQ_CONTROLLER2_SID_EPCS16                       (0x00000014)
0055 #define ALTERA_EPCQ_CONTROLLER2_SID_EPCS64                       (0x00000016)
0056 #define ALTERA_EPCQ_CONTROLLER2_SID_EPCS128                      (0x00000018)
0057
0058 /*
0059  * EPCQ_RD_RDID register description macros
0060  *
0061  * Specific device values obtained from Table 28 of:
0062  *  "Quad-Serial Configuration
0063  *  (EPCQ (www.altera.com/literature/hb/cfg/cfg_cf52012.pdf))
0064  *  Devices Datasheet"
0065  */
0066 #define ALTERA_EPCQ_CONTROLLER2_RDID_MASK                         (0x000000FF)
0067 #define ALTERA_EPCQ_CONTROLLER2_RDID_EPCQ16                       (0x00000015)
0068 #define ALTERA_EPCQ_CONTROLLER2_RDID_EPCQ32                       (0x00000016)
0069 #define ALTERA_EPCQ_CONTROLLER2_RDID_EPCQ64                       (0x00000017)
0070 #define ALTERA_EPCQ_CONTROLLER2_RDID_EPCQ128                      (0x00000018)
0071 #define ALTERA_EPCQ_CONTROLLER2_RDID_EPCQ256                      (0x00000019)
0072 #define ALTERA_EPCQ_CONTROLLER2_RDID_EPCQ512                      (0x00000020)
0073 #define ALTERA_EPCQ_CONTROLLER2_RDID_EPCQ1024                     (0x00000021)
0074
0075 /*
0076  * EPCQ_MEM_OP register description macros
0077  */
0078 #define ALTERA_EPCQ_CONTROLLER2_MEM_OP_CMD_MASK                  (0x00000003)
0079 #define ALTERA_EPCQ_CONTROLLER2_MEM_OP_BULK_ERASE_CMD            (0x00000001)
0080 #define ALTERA_EPCQ_CONTROLLER2_MEM_OP_SECTOR_ERASE_CMD          (0x00000002)
0081 #define ALTERA_EPCQ_CONTROLLER2_MEM_OP_SECTOR_PROTECT_CMD        (0x00000003)
0082 #define ALTERA_EPCQ_CONTROLLER2_MEM_OP_WRITE_ENABLE_CMD          (0x00000004)
0083
0084 /** see datasheet for sector values */
0085 #define ALTERA_EPCQ_CONTROLLER2_MEM_OP_SECTOR_VALUE_MASK         (0x00FFFF00)
0086
0087 /*
0088  * EPCQ_ISR register description macros
0089  */
0090 #define ALTERA_EPCQ_CONTROLLER2_ISR_ILLEGAL_ERASE_MASK           (0x00000001)
0091 #define ALTERA_EPCQ_CONTROLLER2_ISR_ILLEGAL_ERASE_ACTIVE         (0x00000001)
0092
0093 #define ALTERA_EPCQ_CONTROLLER2_ISR_ILLEGAL_WRITE_MASK           (0x00000002)
0094 #define ALTERA_EPCQ_CONTROLLER2_ISR_ILLEGAL_WRITE_ACTIVE         (0x00000002)
0095
0096 /*
0097  * EPCQ_IMR register description macros
0098  */
0099 #define ALTERA_EPCQ_CONTROLLER2_IMR_ILLEGAL_ERASE_MASK           (0x00000001)
0100 #define ALTERA_EPCQ_CONTROLLER2_IMR_ILLEGAL_ERASE_ENABLED        (0x00000001)
0101
0102 #define ALTERA_EPCQ_CONTROLLER2_IMR_ILLEGAL_WRITE_MASK           (0x00000002)
0103 #define ALTERA_EPCQ_CONTROLLER2_IMR_ILLEGAL_WRITE_ENABLED        (0x00000002)
0104
0105 /*
0106  * EPCQ_CHIP_SELECT register description macros
0107  */
0108 #define ALTERA_EPCQ_CHIP1_SELECT        (0x00000001)
0109 #define ALTERA_EPCQ_CHIP2_SELECT        (0x00000002)
0110 #define ALTERA_EPCQ_CHIP3_SELECT        (0x00000003)
0111
0112 #ifdef __cplusplus
0113 extern "C" {
0114 #endif
0115
0116 typedef struct
0117 {
0118   volatile uint32_t rd_status;
0119   volatile uint32_t rd_sid;
0120   volatile uint32_t rd_rdid;
0121   volatile uint32_t mem_op;
0122   volatile uint32_t isr;
0123   volatile uint32_t imr;
0124   volatile uint32_t chip_select;
0125   volatile uint32_t flag_status;
0126   volatile uint32_t dev_id_0;
0127   volatile uint32_t dev_id_1;
0128   volatile uint32_t dev_id_2;
0129   volatile uint32_t dev_id_3;
0130   volatile uint32_t dev_id_4;
0131 }altera_avalon_epcq_regs;
0132
0133 #define EPCQ_REGS \
0134   (( volatile altera_avalon_epcq_regs* )EPCQ_CONTROLLER_AVL_CSR_BASE )
0135 #define EPCQ_MEM \
0136   (( volatile uint8_t* )EPCQ_CONTROLLER_AVL_MEM_BASE )
0137 #define EPCQ_MEM_32 \
0138   (( volatile uint32_t* )EPCQ_CONTROLLER_AVL_MEM_BASE )
0139
0140 void epcq_initialize( void );
0141 int epcq_read_buffer( int offset, uint8_t *dest_addr, int length );
0142 int epcq_write_buffer (
0143   int offset,
0144   const uint8_t* src_addr,
0145   int length,
0146   bool erase
0147 );
0148
0149 #ifdef __cplusplus
0150 }
0151 #endif
0152
0153 #endif