griscv/start/bspsmp.c

0001 /*
0002  * Copyright (c) 2018 embedded brains GmbH & Co. KG
0003  *
0004  * Redistribution and use in source and binary forms, with or without
0005  * modification, are permitted provided that the following conditions
0006  * are met:
0007  * 1. Redistributions of source code must retain the above copyright
0008  *    notice, this list of conditions and the following disclaimer.
0009  * 2. Redistributions in binary form must reproduce the above copyright
0010  *    notice, this list of conditions and the following disclaimer in the
0011  *    documentation and/or other materials provided with the distribution.
0012  *
0013  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
0014  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
0015  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
0016  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
0017  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
0018  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
0019  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
0020  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
0021  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
0022  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
0023  * SUCH DAMAGE.
0024  */
0025
0026 #include <bsp/bootcard.h>
0027 #include <bsp/irq.h>
0028 #include <amba.h>
0029
0030 #include <rtems/score/riscv-utility.h>
0031 #include <rtems/score/smpimpl.h>
0032
0033 static rtems_isr bsp_inter_processor_interrupt( void *v )
0034 {
0035   _SMP_Inter_processor_interrupt_handler(_Per_CPU_Get());
0036 }
0037
0038 void bsp_start_on_secondary_processor(Per_CPU_Control *cpu_self)
0039 {
0040   uint32_t cpu_index_self;
0041
0042   cpu_index_self = _Per_CPU_Get_index(cpu_self);
0043   GRLIB_IrqCtrl_Regs->mask[cpu_index_self] |= 1U << GRLIB_mp_irq;
0044
0045   if (
0046     cpu_index_self < rtems_configuration_get_maximum_processors()
0047       && _SMP_Should_start_processor(cpu_index_self)
0048   ) {
0049     set_csr(mie, MIP_MEIP);
0050     _SMP_Start_multitasking_on_secondary_processor(cpu_self);
0051   } else {
0052     _CPU_Thread_Idle_body(0);
0053   }
0054 }
0055
0056 uint32_t _CPU_SMP_Initialize(void)
0057 {
0058   GRLIB_Cpu_Unmask_interrupt(GRLIB_mp_irq, _CPU_SMP_Get_current_processor());
0059
0060   rtems_interrupt_handler_install(
0061     GRLIB_mp_irq,
0062     "IPI",
0063     RTEMS_INTERRUPT_SHARED,
0064     bsp_inter_processor_interrupt,
0065     NULL
0066   );
0067
0068   return grlib_get_cpu_count(GRLIB_IrqCtrl_Regs);
0069 }
0070
0071 bool _CPU_SMP_Start_processor(uint32_t cpu_index)
0072 {
0073   GRLIB_IrqCtrl_Regs->mpstat = 1U << cpu_index;
0074
0075   return true;
0076 }
0077
0078 void _CPU_SMP_Finalize_initialization(uint32_t cpu_count)
0079 {
0080   (void) cpu_count;
0081 //  set_csr(mie, MIP_MSIP);
0082 }
0083
0084 void _CPU_SMP_Prepare_start_multitasking(void)
0085 {
0086   /* Do nothing */
0087 }
0088
0089 void _CPU_SMP_Send_interrupt(uint32_t target_processor_index)
0090 {
0091
0092   GRLIB_IrqCtrl_Regs->force[target_processor_index] = 1 << GRLIB_mp_irq;
0093
0094 }