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File indexing completed on 2025-05-11 08:24:00

0001 /**
0002  * @file
0003  *
0004  * @ingroup RISCV_IRQ
0005  *
0006  * @brief Interrupt definitions.
0007  */
0008 
0009 /*
0010  * Copyright (c) 2018 embedded brains GmbH & Co. KG
0011  *
0012  * Copyright (c) 2015 University of York.
0013  * Hesham Almatary <hesham@alumni.york.ac.uk>
0014  *
0015  * Redistribution and use in source and binary forms, with or without
0016  * modification, are permitted provided that the following conditions
0017  * are met:
0018  * 1. Redistributions of source code must retain the above copyright
0019  *    notice, this list of conditions and the following disclaimer.
0020  * 2. Redistributions in binary form must reproduce the above copyright
0021  *    notice, this list of conditions and the following disclaimer in the
0022  *    documentation and/or other materials provided with the distribution.
0023  *
0024  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
0025  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
0026  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
0027  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
0028  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
0029  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
0030  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
0031  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
0032  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
0033  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
0034  * SUCH DAMAGE.
0035  */
0036 
0037 #ifndef LIBBSP_RISCV_GRISCV_IRQ_H
0038 #define LIBBSP_RISCV_GRISCV_IRQ_H
0039 
0040 #ifndef ASM
0041 
0042 #include <bsp.h>
0043 
0044 #define RISCV_INTERRUPT_VECTOR_SOFTWARE 0
0045 
0046 #define RISCV_INTERRUPT_VECTOR_TIMER 1
0047 
0048 #define RISCV_INTERRUPT_VECTOR_EXTERNAL(x) ((x) + 2)
0049 
0050 #define RISCV_INTERRUPT_VECTOR_IS_EXTERNAL(x) ((x) >= 2)
0051 
0052 #define RISCV_INTERRUPT_VECTOR_EXTERNAL_TO_INDEX(x) ((x) - 2)
0053 
0054 #define BSP_INTERRUPT_VECTOR_COUNT RISCV_INTERRUPT_VECTOR_EXTERNAL(RISCV_MAXIMUM_EXTERNAL_INTERRUPTS)
0055 
0056 #endif /* ASM */
0057 
0058 #endif /* LIBBSP_RISCV_GRISCV_IRQ_H */