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File indexing completed on 2025-05-11 08:24:00
0001 /*!@file 0002 * 0003 * @brief Initialization code to set up the CPU and call boot_card() 0004 * 0005 * This "BSP" targets the Xilinx Virtex XC5VFX70T and related parts. This 0006 * BSP makes no assumptions on what firmware is loaded into the FPGA. 0007 * 0008 * Provides the .entry section code. This is the first code to run in 0009 * the PPC after download to RAM. Excecution in this case starts at 0010 * 'download_entry'. 0011 * 0012 * The entrypoint 'start' is provided for the case where a bootloader has 0013 * initialized the CPU, and all that remains to do is to set up a C 0014 * environment and call boot_card. 0015 * 0016 * Derived from virtex dlentry and others. 0017 * 0018 * Some portions of this code follow section 3.4 of the PPC440x5 CPU Core User's 0019 * Manual v7.1 from IBM. Other parts were derived from examples provided 0020 * by Xilinx in their ML510 Reference Designs, e.g., ml510_bsb1_design_ppc440. 0021 * See boot.S in standalone/, for example. 0022 * 0023 * References: 0024 * Embedded Processor Block in Virtex-5 FPGAs Reference Guide UG200 (v1.8) 0025 * http://www.xilinx.com/support/documentation/user_guides/ug200.pdf 0026 * 0027 * PowerPC 440x5 Embedded Processor Core User's Manual (Version 7.1) 0028 * https://www-01.ibm.com/chips/techlib/techlib.nsf/products/PowerPC_440_Embedded_Core 0029 * 0030 * @author Richard Claus <claus@SLAC.Stanford.edu> 0031 * 0032 * @date March 4, 2011 -- Created 0033 * 0034 * $Revision: 675 $ 0035 * 0036 * @verbatim Copyright 2011 0037 * by 0038 * The Board of Trustees of the 0039 * Leland Stanford Junior University. 0040 * All rights reserved. 0041 * 0042 * Work supported by the U.S. Department of Energy under contract 0043 * DE-AC03-76SF00515. 0044 * 0045 * Disclaimer Notice 0046 * 0047 * The items furnished herewith were developed under the sponsorship 0048 * of the U.S. Government. Neither the U.S., nor the U.S. D.O.E., nor the 0049 * Leland Stanford Junior University, nor their employees, makes any war- 0050 * ranty, express or implied, or assumes any liability or responsibility 0051 * for accuracy, completeness or usefulness of any information, apparatus, 0052 * product or process disclosed, or represents that its use will not in- 0053 * fringe privately-owned rights. Mention of any product, its manufactur- 0054 * er, or suppliers shall not, nor is it intended to, imply approval, dis- 0055 * approval, or fitness for any particular use. The U.S. and the Univer- 0056 * sity at all times retain the right to use and disseminate the furnished 0057 * items for any purpose whatsoever. Notice 91 02 01 0058 * 0059 * @endverbatim 0060 */ 0061 0062 #include <rtems/asm.h> 0063 #include <rtems/powerpc/powerpc.h> 0064 #include <rtems/powerpc/registers.h> 0065 0066 #define V_TS_SZ_I 0x0290 // V,TS=0(Inst),SIZE=9,TID=0 0067 #define V_TS_SZ_D 0x0390 // V,TS=1(Data),SIZE=9,TID=0 0068 #define WIMG_U_S_0 0x043F // !(U0-3),!W, I,!M,!G,!E,UX,UW,UR,SX,SW,SR 0069 #define WIMG_U_S_1 0x003F // !(U0-3),!W,!I,!M,!G,!E,UX,UW,UR,SX,SW,SR 0070 #define PAGE_SZ 0x10000000 // 256 MB 0071 0072 /* 0073 * The virtex ELF link scripts support some special sections: 0074 * .entry The actual entry point 0075 * .vectors The section containing the interrupt entry veneers. 0076 */ 0077 0078 /* 0079 * Downloaded code loads the vectors separately to 0x00000100, 0080 * so .entry can be over 256 bytes. 0081 * 0082 * The other sections are linked in the following order: 0083 * .entry 0084 * .text 0085 * .data 0086 * .bss 0087 * see linker command file for section placement 0088 * 0089 * The initial stack is set to _ISR_Stack_area_end. 0090 * 0091 * All the entry veneer has to do is to clear the BSS. 0092 */ 0093 0094 .section .entry 0095 0096 PUBLIC_VAR(download_entry) 0097 PUBLIC_VAR(__rtems_entry_point) 0098 SYM(download_entry): 0099 SYM(__rtems_entry_point): 0100 b startupDL /* Entry point used by xmd dow command */ 0101 0102 PUBLIC_VAR (start) 0103 SYM(start): 0104 b startupBL /* Entry point used by bootLoader */ 0105 0106 base_addr: 0107 /*------------------------------------------------------------------- 0108 * Parameters from linker 0109 *-----------------------------------------------------------------*/ 0110 toc_pointer: 0111 .long __got_start 0112 bss_length: 0113 .long __bss_size 0114 bss_addr: 0115 .long __bss_start 0116 stack_top: 0117 .long _ISR_Stack_area_end 0118 0119 0120 .eject 0121 0122 /*------------------------------------------------------------------ 0123 * This code follows section 3.4 of the PPC440x5 CPU Core User's 0124 * Manual. The numbers in the comments refer to the step numbers 0125 * therein. Some of the implementation comes from examples provided 0126 * by Xilinx in their ML510 Reference Designs, e.g., 0127 * ml510_bsb1_design_ppc440. See boot.S in standalone/. 0128 *------------------------------------------------------------------*/ 0129 /*------------------------------------------------------------------ 0130 * This code is designed to accomodate warm restarts, in which the 0131 * application software triggers the restart of the system by branching 0132 * to the following code (either boot or boot1) without causing 0133 * one of the hardware resets: core, chip, system or JTAG (section 0134 * 3.2,3 in the Power PC 440-S Embedded Processor Core User's Manual). 0135 *-----------------------------------------------------------------*/ 0136 0137 /* ----------------------------------------------------------------- 0138 * Setup CPU 0139 *-----------------------------------------------------------------*/ 0140 first: li r0,0 // Clear r0 0141 0142 /* ----------------------------------------------------------------- 0143 * Initialize the memory system. 0144 *------------------------------------------------------------------*/ 0145 iccci r0,r0 // 2. Invalidate instruction cache 0146 dccci r0,r0 // 3. Invalidate data cache 0147 msync // 4. Force in-progress data PLB ops to complete 0148 0149 mfdbcr0 r2 // 5. Disable all debug events 0150 lis r3,0x8100 0151 and r2,r2,r3 // Ignore EDM,TRAP to allow XMD use 0152 mtdbcr0 r2 0153 li r2,-1 0154 mtdbsr r2 // 6. Initialize all debug event status 0155 0156 /*------------------------------------------------------------------ 0157 * Set Core Configuration Register 0 as follows: 0158 * sum: 0x00206000 0159 * bit 1 off Parity Recovery Enable 0160 * bit 4 off Cache Read Parity Enable 0161 * bit 10 on Disable Store Gathering 0162 * bit 11 off Disable APU Instruction Broadcast 0163 * bit 16 off Disable Trace Broadcast 0164 * bit 17:18 on Specifies behaviour of icbt,dcbt/dcbtst insts 0165 * bit 23 off Force Load/Store Alignment 0166 * bit 28:29 off Instruction Cache Speculative Line Count 0167 * bit 30:31 off Instruction Cache Speculative Line Threshold 0168 * NB: UG200/pg 21: Spec. prefetching must be disabled 0169 *------------------------------------------------------------------*/ 0170 0171 lis r2, 0x00206000@h // 7. Set CCR0: DSTG 0172 ori r2,r2,0x00206000@l // Set CCR0: GDCBT, GICBT 0173 mtccr0 r2 // Configure CCR0 0174 0175 mtspr PPC440_CCR1,r0 // 8. Clear CCR1 0176 0177 /*------------------------------------------------------------------ 0178 * 9. Configure cache regions 0179 *------------------------------------------------------------------*/ 0180 mtspr PPC440_INV0,r0 0181 mtspr PPC440_INV1,r0 0182 mtspr PPC440_INV2,r0 0183 mtspr PPC440_INV3,r0 0184 mtspr PPC440_DNV0,r0 0185 mtspr PPC440_DNV1,r0 0186 mtspr PPC440_DNV2,r0 0187 mtspr PPC440_DNV3,r0 0188 mtspr PPC440_ITV0,r0 0189 mtspr PPC440_ITV1,r0 0190 mtspr PPC440_ITV2,r0 0191 mtspr PPC440_ITV3,r0 0192 mtspr PPC440_DTV0,r0 0193 mtspr PPC440_DTV1,r0 0194 mtspr PPC440_DTV2,r0 0195 mtspr PPC440_DTV3,r0 0196 0197 /*------------------------------------------------------------------ 0198 * Cache victim limits 0199 * floors 0, ceiling max to use the entire cache -- nothing locked 0200 *------------------------------------------------------------------*/ 0201 lis r2, 0x0001f800@h 0202 ori r2,r2,0x0001f800@l 0203 mtspr PPC440_IVLIM,r2 0204 mtspr PPC440_DVLIM,r2 0205 0206 /*------------------------------------------------------------------ 0207 * Configure instruction and data cache regions: 0208 * Set up register constants (r6,r7), page index (r5), address 0209 * variable (r4), EPN_V_TS bits (r3) 0210 * 0211 * Word 0 bits: 0xX0000290, 0xX0000390 0212 * Bits Field Inst Data Description 0213 * 0:21 EPN 0-15 0-15 Effective Page Number 0214 * 22 V 1 1 Valid 0215 * 23 TS 0 1 Translation Address Space 0216 * 24:27 SIZE 9 9 Page Size (9 = 256 MB) 0217 * 38:31 TPAR 0 0 Tag Parity 0218 * 32:39 TID 0 0 Translation ID (in the MMUCR) 0219 * 0220 * Word 1 bits: 0x00000000, 0x00000000 0221 * Bits Field Inst Data Description 0222 * 0:21 RPN 0 0 Real Page Number 0223 * 22:23 PAR1 0 0 Parity for TLB word 1 0224 * 28:31 ERPN 0 0 Extended Real Page Number 0225 * 0226 * Word 2 bits: 0x0000043f, 0x00000c3f 0227 * Bits Field Inst Data Description 0228 * 0: 1 PAR2 0 0 Parity for TLB word 2 0229 * 16 U0 0 0 User-Defineable Storage Attribute 0 0230 * 17 U1 0 0 User-Defineable Storage Attribute 1 0231 * 18 U2 0 0 User-Defineable Storage Attribute 2 0232 * 19 U3 0 0 User-Defineable Storage Attribute 3 0233 * 20 W 0 0 Write-Through 0234 * 21 I 1 1 Caching Inhibited 0235 * 22 M 0 0 Memory Coherence Required 0236 * 23 G 0 0 Guarded 0237 * 24 E 0 0 Endian 0238 * 26 UX 1 1 User State Execute Enable 0239 * 27 UW 1 1 User State Write Enable 0240 * 28 UR 1 1 User State Read Enable 0241 * 29 SX 1 1 Supervisor State Execute Enable 0242 * 30 SW 1 1 Supervisor State Write Enable 0243 * 31 SR 1 1 Supervisor State Read Enable 0244 *------------------------------------------------------------------*/ 0245 0246 mtspr PPC440_MMUCR,r0 // 10a. Clear MMUCR 0247 li r7,WIMG_U_S_1 // Word 2: Pages are NOT cache inhibited 0248 lis r6, PAGE_SZ@h // Page size constant 0249 ori r6,r6,PAGE_SZ@l 0250 mr r5,r0 // TLB entry index 0251 mr r4,r0 // Initialize RPN to zero 0252 mflr r28 // Save return address 0253 bl tlbSetup // 10b. Set up the TLBs 0254 mtlr r28 // Restore return address 0255 0256 /*------------------------------------------------------------------ 0257 * Select whether Wait Enable, interrupts/exceptions and which address 0258 * spaces should be enabled when application starts 0259 *------------------------------------------------------------------*/ 0260 lis r3, 0x00000000@h // 10d. MSR[IS]=0 MSR[DS]=0 0261 ori r3,r3,0x00000000@l 0262 mtsrr1 r3 0263 mtsrr0 r28 // Return address 0264 rfi // Context synchronize to invalidate shadow TLB contents 0265 0266 0267 /*------------------------------------------------------------------- 0268 * Entry point used when downloaded, e.g. through XMD 0269 *------------------------------------------------------------------*/ 0270 startupDL: 0271 /*------------------------------------------------------------------- 0272 * Do initialization up to the point where a context sync is required 0273 *------------------------------------------------------------------*/ 0274 bl first // Do first things first 0275 0276 /*------------------------------------------------------------------- 0277 * 11. Tell the processor where the exception vector table will be 0278 *------------------------------------------------------------------*/ 0279 .extern SYM(__vectors) 0280 lis r1, __vectors@h /* set EVPR exc. vector prefix */ 0281 mtspr BOOKE_IVPR,r1 0282 0283 /*------------------------------------------------------------------ 0284 * Set up default exception and interrupt vectors 0285 *------------------------------------------------------------------*/ 0286 li r1,0 0287 mtivor0 r1 0288 addi r1,r1,0x10 0289 mtivor1 r1 0290 addi r1,r1,0x10 0291 mtivor2 r1 0292 addi r1,r1,0x10 0293 mtivor3 r1 0294 addi r1,r1,0x10 0295 mtivor4 r1 0296 addi r1,r1,0x10 0297 mtivor5 r1 0298 addi r1,r1,0x10 0299 mtivor6 r1 0300 addi r1,r1,0x10 0301 mtivor7 r1 0302 addi r1,r1,0x10 0303 mtivor8 r1 0304 addi r1,r1,0x10 0305 mtivor9 r1 0306 addi r1,r1,0x10 0307 mtivor10 r1 0308 addi r1,r1,0x10 0309 mtivor11 r1 0310 addi r1,r1,0x10 0311 mtivor12 r1 0312 addi r1,r1,0x10 0313 mtivor13 r1 0314 addi r1,r1,0x10 0315 mtivor14 r1 0316 addi r1,r1,0x10 0317 mtivor15 r1 0318 0319 /*------------------------------------------------------------------ 0320 * 12. Configure debug facilities 0321 *------------------------------------------------------------------*/ 0322 mtdbcr1 r0 0323 mtdbcr2 r0 0324 mtiac1 r0 0325 mtiac2 r0 0326 mtiac3 r0 0327 mtiac4 r0 0328 mtdac1 r0 0329 mtdac2 r0 0330 mtdvc1 r0 0331 mtdvc2 r0 0332 mfdbcr0 r2 // Freeze timers on debug events 0333 ori r2,r2,0x0001 0334 mtdbcr0 r2 0335 isync 0336 0337 /*------------------------------------------------------------------- 0338 * 13. Configure timer facilities 0339 *------------------------------------------------------------------*/ 0340 mtdec r0 // Clear Decrementer to prevent exception 0341 mttbl r0 // Clear Timebase to prevent Fixed Interval.. 0342 mttbu r0 // ..timer and Watchdog Timer exceptions 0343 mtpit r0 // Programmable interval timer 0344 li r2,-1 // -1 to clear TSR 0345 mttsr r2 // Timer status register 0346 0347 /*------------------------------------------------------------------- 0348 * Clear out stale values in certain registers to avoid confusion 0349 *------------------------------------------------------------------*/ 0350 mtcrf 0xff,r0 // Need for simulation 0351 mtctr r0 // Counter register 0352 mtxer r0 // Fixed-point exception register 0353 mtesr r0 // Exception syndrome register 0354 mtdear r0 // Data exception address register 0355 mtmcsr r0 // Machine check syndrome register 0356 0357 /* Fall through */ 0358 0359 /* ------------------------------------------------------------------- 0360 * If a bootloader has run that has already initialized the CPU, 0361 * which among other things has loaded this code into memory and 0362 * jumped to start above, the initialization above does not need 0363 * to be redone. Execution thus resumes here. 0364 *------------------------------------------------------------------*/ 0365 0366 startupBL: 0367 /*------------------------------------------------------------------- 0368 * Load the parameter table base address 0369 *------------------------------------------------------------------*/ 0370 lis r1, base_addr@h 0371 ori r1,r1,base_addr@l 0372 0373 /*------------------------------------------------------------------- 0374 * Setup stack for RTEMS and call boot_card(). From this 0375 * point forward registers will be used in accordance with the 0376 * PowerPC EABI. 0377 * 0378 * boot_card() supervises the initialization of RTEMS and the C 0379 * library. It calls bsp_start(), bsp_predriver_hook(), etc. 0380 *------------------------------------------------------------------*/ 0381 lwz r2,toc_pointer-base_addr(r1) /* set r2 to toc */ 0382 lwz r1,stack_top-base_addr(r1) /* set r1 to stack_top */ 0383 0384 /* Align as required by ABI */ 0385 li r3,PPC_STACK_ALIGNMENT-1 0386 andc r1,r1,r3 0387 0388 /*------------------------------------------------------------------- 0389 * Set up r2 and r13. Upon entry r1 must have a nonzero value 0390 * as it will be stored in an "init done" flag. Stupid but true. 0391 * r1 must also be set up as a stack pointer as __eabi() jumps 0392 * to __init() which has a standard function prolog. 0393 *------------------------------------------------------------------*/ 0394 bl __eabi /* setup EABI and SYSV environment */ 0395 0396 /*------------------------------------------------------------------- 0397 * Zero the .bss, .sbss and .sbss2 sections. 0398 * Must have r2 and r13 properly set. 0399 *------------------------------------------------------------------*/ 0400 bl zero_bss /* Assume Bank regs set up..., cache etc. */ 0401 0402 /*------------------------------------------------------------------- 0403 * Create a minimal stack frame for this code, the caller of boot_card(). 0404 *------------------------------------------------------------------*/ 0405 addi r1,r1,-PPC_MINIMUM_STACK_FRAME_SIZE 0406 0407 xor r3,r3,r3 /* Clear r3 */ 0408 stw r3,0(r1) /* Clear stack chain */ 0409 stw r3,4(r1) 0410 stw r3,8(r1) 0411 stw r3,12(r1) 0412 lis r5,environ@ha 0413 la r5,environ@l(r5) /* environp */ 0414 0415 /*------------------------------------------------------------------- 0416 * Call boot_card() with its arguments, the command-line pointer and 0417 * the argument count, set to NULL. 0418 *------------------------------------------------------------------*/ 0419 li r4,0 /* argv */ 0420 li r3,0 /* argc */ 0421 .extern SYM (boot_card) 0422 b SYM (boot_card) /* call the first C routine */ 0423 0424 0425 .eject 0426 0427 /*------------------------------------------------------------------ 0428 * Set up TLB entries: 2 entries are needed for the same 256MB page 0429 * one for instruction memory and the other for data memory. 0430 * (TS bit=0 for instructions) 0431 *------------------------------------------------------------------*/ 0432 tlbSetup: 0433 1: ori r3,r4,V_TS_SZ_I // Fold V_TS_SZ in with EPN=RPN 0434 tlbwe r3,r5,0 // Word 0: EPN_V_TS_SZ (Instructions) 0435 tlbwe r4,r5,1 // Word 1: RPN_ERPN 0436 tlbwe r7,r5,2 // Word 2: WIMG_U_S 0437 ori r3,r4,V_TS_SZ_D // Fold V_TS_SZ in with EPN=RPN 0438 addi r5,r5,1 // Next TLB entry 0439 tlbwe r3,r5,0 // Word 0: EPN_V_TS_SZ (Data) 0440 tlbwe r4,r5,1 // Word 1: RPN_ERPN 0441 tlbwe r7,r5,2 // Word 2: WIMG_U_S 0442 add r4,r4,r6 // Increment RPN to next 256MB block 0443 addi r5,r5,1 // Next TLB entry 0444 cmpwi r5,32 // Done yet? 0445 bne 1b 0446 li r0,0 0447 2: // Zero out index 32-63 TLB entries 0448 tlbwe r0,r5,0 0449 tlbwe r0,r5,1 0450 tlbwe r0,r5,2 0451 addi r5,r5,1 0452 cmpwi r5,64 0453 bne 2b 0454 0455 blr
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