powerpc/virtex5/README.md

0001 virtex5
0002 =======
0003 Adapted from virtex BSP
0004
0005 ```
0006 BSP NAME:           virtex5
0007 BOARD:              N/A
0008 BUS:                N/A
0009 CPU FAMILY:         ppc
0010 CPU:                PowerPC 440x5
0011 COPROCESSORS:       N/A
0012 MODE:               32 bit mode
0013
0014 DEBUG MONITOR:
0015 ```
0016
0017 PERIPHERALS
0018 -----------
0019 ```
0020 TIMERS:             440 internal
0021 SERIAL PORTS:       none
0022 REAL-TIME CLOCK:    none
0023 DMA:                Xilinx virtex internal
0024 VIDEO:              none
0025 SCSI:               none
0026 NETWORKING:         none
0027 ```
0028
0029 DRIVER INFORMATION
0030 ------------------
0031 ```
0032 CLOCK DRIVER:       PPC Decrementer
0033 IOSUPP DRIVER:      N/A
0034 SHMSUPP:            N/A
0035 TIMER DRIVER:       N/A
0036 TTY DRIVER:         N/A
0037 ```
0038
0039 STDIO
0040 -----
0041 ```
0042 PORT:               N/A
0043 ELECTRICAL:         N/A
0044 BAUD:               N/A
0045 BITS PER CHARACTER: N/A
0046 PARITY:             N/A
0047 STOP BITS:          N/A
0048 ```
0049
0050 Board description
0051 -----------------
0052 clock rate:     465 MHz
0053 ROM:            N/A
0054 RAM:            4GByte DRAM
0055
0056 Virtex only supports single processor operations.
0057
0058 Porting
0059 -------
0060 This board support package is written for a naked Virtex 5/PPC FPGA
0061 system. The rough features of such a board are described above.
0062 The BSP itself makes no assumptions on what is loaded in the FPGA,
0063 other than that the CPU has access to some memory, either on-board
0064 or external, from which code can be run.
0065
0066 This BSP has been constructed so that an application of both firmware
0067 and software can be layered on top of it by supplying implementations
0068 for the various 'weak' symbols.  These symbols are prefaced with the
0069 term 'app_'.  Applications can thus be built outside of the RTEMS
0070 directory tree by linking with the appropriate libraries.
0071
0072 The linkcmds file describes the memory layout.  Included in this
0073 definition is a section of memory named MsgArea.  Output sent to
0074 stdout is recorded in this area and can be dumped using the JTAG
0075 interface, for example.
0076
0077 For adapting this BSP to other boards, the following files should be
0078 modified:
0079
0080 - c/src/lib/libbsp/powerpc/virtex5/startup/linkcmds
0081         for the memory layout required
0082
0083 - c/src/lib/libbsp/powerpc/virtex5/startup/bspstart.c
0084         Here you can select the clock source for the timers and the
0085         serial interface (system clock or external clock pin), the
0086         clock rates, etc.
0087
0088 - c/src/lib/libbsp/powerpc/virtex5/include/bsp.h
0089         some BSP-related constants
0090
0091 - c/src/lib/libbsp/powerpc/virtex5/*
0092         well, they should be generic, so there _should_ be no reason
0093         to mess around there (but who knows...)