Warning, /bsps/powerpc/virtex4/README.md is written in an unsupported language. File is not indexed.
0001 virtex4
0002 =======
0003 Adapted from virtex BSP
0004
0005 ```
0006 BSP NAME: virtex4
0007 BOARD: N/A
0008 BUS: N/A
0009 CPU FAMILY: ppc
0010 CPU: PowerPC 405D5
0011 COPROCESSORS: N/A
0012 MODE: 32 bit mode
0013
0014 DEBUG MONITOR:
0015 ```
0016
0017 PERIPHERALS
0018 -----------
0019 ```
0020 TIMERS: 405 internal
0021 SERIAL PORTS: none
0022 REAL-TIME CLOCK: none
0023 DMA: Xilinx virtex internal
0024 VIDEO: none
0025 SCSI: none
0026 NETWORKING: none
0027 ```
0028
0029 DRIVER INFORMATION
0030 ------------------
0031 ```
0032 CLOCK DRIVER: PPC Decrementer
0033 IOSUPP DRIVER: N/A
0034 SHMSUPP: N/A
0035 TIMER DRIVER: N/A
0036 TTY DRIVER: N/A
0037 ```
0038
0039 STDIO
0040 -----
0041 PORT: N/A
0042 ELECTRICAL: N/A
0043 BAUD: N/A
0044 BITS PER CHARACTER: N/A
0045 PARITY: N/A
0046 STOP BITS: N/A
0047 ```
0048
0049 Board description
0050 -----------------
0051 ```
0052 clock rate: 350 MHz
0053 ROM: N/A
0054 RAM: 128MByte DRAM
0055 ```
0056
0057 Virtex only supports single processor operations.
0058
0059 Porting
0060 -------
0061 This board support package is written for a naked Virtex 4/PPC FPGA
0062 system. The rough features of such a board are described above.
0063 The BSP itself makes no assumptions on what is loaded in the FPGA,
0064 other than that the CPU has access to some memory, either on-board
0065 or external, from which code can be run.
0066
0067 This BSP has been constructed so that an application of both firmware
0068 and software can be layered on top of it by supplying implementations
0069 for the various 'weak' symbols. These symbols are prefaced with the
0070 term 'app_'. Applications can thus be built outside of the RTEMS
0071 directory tree by linking with the appropriate libraries.
0072
0073 The linkcmds file describes the memory layout. Included in this
0074 definition is a section of memory named MsgArea. Output sent to
0075 stdout is recorded in this area and can be dumped using the JTAG
0076 interface, for example.
0077
0078 For adapting this BSP to other boards, the following files should be
0079 modified:
0080
0081 - c/src/lib/libbsp/powerpc/virtex4/startup/linkcmds
0082 for the memory layout required
0083
0084 - c/src/lib/libbsp/powerpc/virtex4/startup/bspstart.c
0085 Here you can select the clock source for the timers and the
0086 serial interface (system clock or external clock pin), the
0087 clock rates, etc.
0088
0089 - c/src/lib/libbsp/powerpc/virtex4/include/bsp.h
0090 some BSP-related constants
0091
0092 - c/src/lib/libbsp/powerpc/virtex4/*
0093 well, they should be generic, so there _should_ be no reason
0094 to mess around there (but who knows...)
