virtex/include/xparameters_dflt.h

0001 /*******************************************************************
0002 *
0003 * CAUTION: This file is automatically generated by libgen.
0004 * Version: Xilinx EDK 8.2.02 EDK_Im_Sp2.4
0005 * DO NOT EDIT.
0006 *
0007 * Copyright (c) 2005 Xilinx, Inc.  All rights reserved.
0008 *
0009 * Description: Driver parameters
0010 *
0011 *******************************************************************/
0012
0013 #define STDIN_BASEADDRESS 0x40600000
0014 #define STDOUT_BASEADDRESS 0x40600000
0015
0016 /******************************************************************/
0017
0018 /* Definitions for driver PLBARB */
0019 #define XPAR_XPLBARB_NUM_INSTANCES 1
0020
0021 /* Definitions for peripheral PLB */
0022 #define XPAR_PLB_BASEADDR 0x00000000
0023 #define XPAR_PLB_HIGHADDR 0x00000000
0024 #define XPAR_PLB_DEVICE_ID 0
0025 #define XPAR_PLB_PLB_NUM_MASTERS 3
0026
0027
0028 /******************************************************************/
0029
0030 /* Definitions for driver OPBARB */
0031 #define XPAR_XOPBARB_NUM_INSTANCES 1
0032
0033 /* Definitions for peripheral OPB */
0034 #define XPAR_OPB_BASEADDR 0xFFFFFFFF
0035 #define XPAR_OPB_HIGHADDR 0x00000000
0036 #define XPAR_OPB_DEVICE_ID 0
0037 #define XPAR_OPB_NUM_MASTERS 1
0038
0039
0040 /******************************************************************/
0041
0042 /* Definitions for driver UARTLITE */
0043 #define XPAR_XUARTLITE_NUM_INSTANCES 1
0044
0045 /* Definitions for peripheral CONSOLE */
0046 #define XPAR_CONSOLE_BASEADDR 0x40600000
0047 #define XPAR_CONSOLE_HIGHADDR 0x4060FFFF
0048 #define XPAR_CONSOLE_DEVICE_ID 0
0049 #define XPAR_CONSOLE_BAUDRATE 115200
0050 #define XPAR_CONSOLE_USE_PARITY 0
0051 #define XPAR_CONSOLE_ODD_PARITY 0
0052 #define XPAR_CONSOLE_DATA_BITS 8
0053
0054
0055 /******************************************************************/
0056
0057 /* Definitions for driver GPIO */
0058 #define XPAR_XGPIO_NUM_INSTANCES 3
0059
0060 /* Definitions for peripheral LEDS */
0061 #define XPAR_LEDS_BASEADDR 0x40000000
0062 #define XPAR_LEDS_HIGHADDR 0x4000FFFF
0063 #define XPAR_LEDS_DEVICE_ID 0
0064 #define XPAR_LEDS_INTERRUPT_PRESENT 0
0065 #define XPAR_LEDS_IS_DUAL 0
0066
0067
0068 /* Definitions for peripheral PBLEDS */
0069 #define XPAR_PBLEDS_BASEADDR 0x40020000
0070 #define XPAR_PBLEDS_HIGHADDR 0x4002FFFF
0071 #define XPAR_PBLEDS_DEVICE_ID 1
0072 #define XPAR_PBLEDS_INTERRUPT_PRESENT 0
0073 #define XPAR_PBLEDS_IS_DUAL 0
0074
0075
0076 /* Definitions for peripheral PUSHBUTTONS */
0077 #define XPAR_PUSHBUTTONS_BASEADDR 0x40040000
0078 #define XPAR_PUSHBUTTONS_HIGHADDR 0x4004FFFF
0079 #define XPAR_PUSHBUTTONS_DEVICE_ID 2
0080 #define XPAR_PUSHBUTTONS_INTERRUPT_PRESENT 1
0081 #define XPAR_PUSHBUTTONS_IS_DUAL 0
0082
0083
0084 /******************************************************************/
0085
0086 /* Definitions for driver TMRCTR */
0087 #define XPAR_XTMRCTR_NUM_INSTANCES 1
0088
0089 /* Definitions for peripheral OPBTIMER */
0090 #define XPAR_OPBTIMER_BASEADDR 0x41C00000
0091 #define XPAR_OPBTIMER_HIGHADDR 0x41C0FFFF
0092 #define XPAR_OPBTIMER_DEVICE_ID 0
0093
0094
0095 /******************************************************************/
0096
0097 #define XPAR_INTC_MAX_NUM_INTR_INPUTS 3
0098 #define XPAR_XINTC_HAS_IPR 1
0099 #define XPAR_XINTC_USE_DCR 0
0100 /* Definitions for driver INTC */
0101 #define XPAR_XINTC_NUM_INSTANCES 1
0102
0103 /* Definitions for peripheral INTC */
0104 #define XPAR_INTC_BASEADDR 0x41200000
0105 #define XPAR_INTC_HIGHADDR 0x4120FFFF
0106 #define XPAR_INTC_DEVICE_ID 0
0107 #define XPAR_INTC_KIND_OF_INTR 0x00000000
0108
0109
0110 /******************************************************************/
0111
0112 #define XPAR_INTC_SINGLE_BASEADDR 0x41200000
0113 #define XPAR_INTC_SINGLE_HIGHADDR 0x4120FFFF
0114 #define XPAR_INTC_SINGLE_DEVICE_ID XPAR_INTC_DEVICE_ID
0115 #define XPAR_OPBTIMER_INTERRUPT_MASK 0X000001
0116 #define XPAR_INTC_OPBTIMER_INTERRUPT_INTR 0
0117 #define XPAR_ETHERNET_IP2INTC_IRPT_MASK 0X000002
0118 #define XPAR_INTC_ETHERNET_IP2INTC_IRPT_INTR 1
0119 #define XPAR_PUSHBUTTONS_IP2INTC_IRPT_MASK 0X000004
0120 #define XPAR_INTC_PUSHBUTTONS_IP2INTC_IRPT_INTR 2
0121
0122 /******************************************************************/
0123
0124 /* Definitions for driver DDR */
0125 #define XPAR_XDDR_NUM_INSTANCES 1
0126
0127 /* Definitions for peripheral DDR_SDRAM_64MX32 */
0128 #define XPAR_DDR_SDRAM_64MX32_ECC_BASEADDR 0xFFFFFFFF
0129 #define XPAR_DDR_SDRAM_64MX32_ECC_HIGHADDR 0x00000000
0130 #define XPAR_DDR_SDRAM_64MX32_DEVICE_ID 0
0131 #define XPAR_DDR_SDRAM_64MX32_INCLUDE_ECC_INTR 0
0132
0133
0134 /******************************************************************/
0135
0136 /* Definitions for peripheral DDR_SDRAM_64MX32 */
0137 #define XPAR_DDR_SDRAM_64MX32_MEM0_BASEADDR 0x00000000
0138 #define XPAR_DDR_SDRAM_64MX32_MEM0_HIGHADDR 0x03FFFFFF
0139
0140 /******************************************************************/
0141
0142
0143 /* Definitions for peripheral HARD_TEMAC_0 */
0144 #define XPAR_HARD_TEMAC_0_PHY_TYPE 1
0145
0146
0147 /******************************************************************/
0148
0149 /* Definitions for driver TEMAC */
0150 #define XPAR_XTEMAC_NUM_INSTANCES 1
0151
0152 /* Definitions for peripheral ETHERNET */
0153 #define XPAR_ETHERNET_DEVICE_ID 0
0154 #define XPAR_ETHERNET_BASEADDR 0x81200000
0155 #define XPAR_ETHERNET_HIGHADDR 0x8120FFFF
0156 #define XPAR_ETHERNET_RXFIFO_DEPTH 32768
0157 #define XPAR_ETHERNET_TXFIFO_DEPTH 32768
0158 #define XPAR_ETHERNET_MAC_FIFO_DEPTH 64
0159 #define XPAR_ETHERNET_DMA_TYPE 1
0160 #define XPAR_ETHERNET_TX_DRE_TYPE 0
0161 #define XPAR_ETHERNET_RX_DRE_TYPE 0
0162 #define XPAR_ETHERNET_INCLUDE_TX_CSUM 0
0163 #define XPAR_ETHERNET_INCLUDE_RX_CSUM 0
0164
0165
0166 /******************************************************************/
0167
0168
0169 /* Definitions for peripheral FLASH */
0170 #define XPAR_FLASH_NUM_BANKS_MEM 1
0171
0172
0173 /******************************************************************/
0174
0175 /* Definitions for peripheral FLASH */
0176 #define XPAR_FLASH_MEM0_BASEADDR 0x06000000
0177 #define XPAR_FLASH_MEM0_HIGHADDR 0x067FFFFF
0178
0179 /******************************************************************/
0180
0181
0182 /* Definitions for peripheral PLB_BRAM_IF_CNTLR_1 */
0183 #define XPAR_PLB_BRAM_IF_CNTLR_1_BASEADDR 0xffff8000
0184 #define XPAR_PLB_BRAM_IF_CNTLR_1_HIGHADDR 0xffffffff
0185
0186
0187 /******************************************************************/
0188
0189 #define XPAR_CPU_PPC405_CORE_CLOCK_FREQ_HZ 300000000
0190
0191 /******************************************************************/
0192