virtex/include/xiltemac.h

0001 /*
0002  * Driver for plb inteface of the xilinx temac 3.00a
0003  *
0004  * Author: Keith Robertson <kjrobert@alumni.uwaterloo.ca>
0005  * Copyright (c) 2007 Linn Products Ltd, Scotland.
0006  *
0007  * The license and distribution terms for this file may be
0008  * found in the file LICENSE in this distribution or at
0009  * http://www.rtems.org/license/LICENSE.
0010  *
0011  */
0012
0013 #ifndef _XILINX_TEMAC_
0014 #define _XILINX_TEMAC_
0015 #include <rtems/irq.h>
0016
0017
0018 #define XILTEMAC_DRIVER_PREFIX   "xiltemac"
0019
0020 #define DRIVER_PREFIX XILTEMAC_DRIVER_PREFIX
0021
0022
0023 /** IPIF interrupt and reset registers
0024  */
0025 #define XTE_DISR_OFFSET  0x00000000  /**< Device interrupt status */
0026 #define XTE_DIPR_OFFSET  0x00000004  /**< Device interrupt pending */
0027 #define XTE_DIER_OFFSET  0x00000008  /**< Device interrupt enable */
0028 #define XTE_DIIR_OFFSET  0x00000018  /**< Device interrupt ID */
0029 #define XTE_DGIE_OFFSET  0x0000001C  /**< Device global interrupt enable */
0030 #define XTE_IPISR_OFFSET 0x00000020  /**< IP interrupt status */
0031 #define XTE_IPIER_OFFSET 0x00000028  /**< IP interrupt enable */
0032 #define XTE_DSR_OFFSET   0x00000040  /**< Device software reset (write) */
0033
0034 /** IPIF transmit fifo
0035  */
0036 #define XTE_PFIFO_TX_BASE_OFFSET    0x00002000  /**< Packet FIFO Tx channel */
0037 #define XTE_PFIFO_TX_VACANCY_OFFSET 0x00002004  /**< Packet Fifo Tx Vacancy */
0038 #define XTE_PFIFO_TX_DATA_OFFSET    0x00002100  /**< IPIF Tx packet fifo port */
0039
0040 /** IPIF receive fifo
0041  */
0042 #define XTE_PFIFO_RX_BASE_OFFSET    0x00002010  /**< Packet FIFO Rx channel */
0043 #define XTE_PFIFO_RX_VACANCY_OFFSET 0x00002014  /**< Packet Fifo Rx Vacancy */
0044 #define XTE_PFIFO_RX_DATA_OFFSET    0x00002200  /**< IPIF Rx packet fifo port */
0045
0046 /** IPIF fifo masks
0047  */
0048 #define XTE_PFIFO_COUNT_MASK     0x00FFFFFF
0049
0050 /** IPIF transmit and recieve DMA offsets
0051  */
0052 #define XTE_DMA_SEND_OFFSET      0x00002300  /**< DMA Tx channel */
0053 #define XTE_DMA_RECV_OFFSET      0x00002340  /**< DMA Rx channel */
0054
0055 /** IPIF IPIC_TO_TEMAC Core Registers
0056  */
0057 #define XTE_CR_OFFSET           0x00001000  /**< Control */
0058 #define XTE_TPLR_OFFSET         0x00001004  /**< Tx packet length (FIFO) */
0059 #define XTE_TSR_OFFSET          0x00001008  /**< Tx status (FIFO) */
0060 #define XTE_RPLR_OFFSET         0x0000100C  /**< Rx packet length (FIFO) */
0061 #define XTE_RSR_OFFSET          0x00001010  /**< Receive status */
0062 #define XTE_IFGP_OFFSET         0x00001014  /**< Interframe gap */
0063 #define XTE_TPPR_OFFSET         0x00001018  /**< Tx pause packet */
0064
0065 /** TEMAC Core Registers
0066  * These are registers defined within the device's hard core located in the
0067  * processor block. They are accessed with the host interface. These registers
0068  * are addressed offset by XTE_HOST_IPIF_OFFSET or by the DCR base address
0069  * if so configured.
0070  */
0071 #define XTE_HOST_IPIF_OFFSET    0x00003000  /**< Offset of host registers when
0072                                                  memory mapped into IPIF */
0073 #define XTE_ERXC0_OFFSET        (XTE_HOST_IPIF_OFFSET + 0x00000200)  /**< Rx configuration word 0 */
0074 #define XTE_ERXC1_OFFSET        (XTE_HOST_IPIF_OFFSET + 0x00000240)  /**< Rx configuration word 1 */
0075 #define XTE_ETXC_OFFSET         (XTE_HOST_IPIF_OFFSET + 0x00000280)  /**< Tx configuration */
0076 #define XTE_EFCC_OFFSET         (XTE_HOST_IPIF_OFFSET + 0x000002C0)  /**< Flow control configuration */
0077 #define XTE_ECFG_OFFSET         (XTE_HOST_IPIF_OFFSET + 0x00000300)  /**< EMAC configuration */
0078 #define XTE_EGMIC_OFFSET        (XTE_HOST_IPIF_OFFSET + 0x00000320)  /**< RGMII/SGMII configuration */
0079 #define XTE_EMC_OFFSET          (XTE_HOST_IPIF_OFFSET + 0x00000340)  /**< Management configuration */
0080 #define XTE_EUAW0_OFFSET        (XTE_HOST_IPIF_OFFSET + 0x00000380)  /**< Unicast address word 0 */
0081 #define XTE_EUAW1_OFFSET        (XTE_HOST_IPIF_OFFSET + 0x00000384)  /**< Unicast address word 1 */
0082 #define XTE_EMAW0_OFFSET        (XTE_HOST_IPIF_OFFSET + 0x00000388)  /**< Multicast address word 0 */
0083 #define XTE_EMAW1_OFFSET        (XTE_HOST_IPIF_OFFSET + 0x0000038C)  /**< Multicast address word 1 */
0084 #define XTE_EAFM_OFFSET         (XTE_HOST_IPIF_OFFSET + 0x00000390)  /**< Promisciuous mode */
0085 #define XTE_EIRS_OFFSET         (XTE_HOST_IPIF_OFFSET + 0x000003A0)  /**< IRstatus */
0086 #define XTE_EIREN_OFFSET        (XTE_HOST_IPIF_OFFSET + 0x000003A4)  /**< IRenable */
0087 #define XTE_EMIID_OFFSET        (XTE_HOST_IPIF_OFFSET + 0x000003B0)  /**< MIIMwrData */
0088 #define XTE_EMIIC_OFFSET        (XTE_HOST_IPIF_OFFSET + 0x000003B4)  /**< MiiMcnt */
0089
0090 /* Register masks. The following constants define bit locations of various
0091  * control bits in the registers. Constants are not defined for those registers
0092  * that have a single bit field representing all 32 bits. For further
0093  * information on the meaning of the various bit masks, refer to the HW spec.
0094  */
0095
0096 /** Interrupt status bits for top level interrupts
0097  *  These bits are associated with the XTE_DISR_OFFSET, XTE_DIPR_OFFSET,
0098  *  and XTE_DIER_OFFSET registers.
0099  */
0100 #define XTE_DXR_SEND_FIFO_MASK          0x00000040 /**< Send FIFO channel */
0101 #define XTE_DXR_RECV_FIFO_MASK          0x00000020 /**< Receive FIFO channel */
0102 #define XTE_DXR_RECV_DMA_MASK           0x00000010 /**< Receive DMA channel */
0103 #define XTE_DXR_SEND_DMA_MASK           0x00000008 /**< Send DMA channel */
0104 #define XTE_DXR_CORE_MASK               0x00000004 /**< Core */
0105 #define XTE_DXR_DPTO_MASK               0x00000002 /**< Data phase timeout */
0106 #define XTE_DXR_TERR_MASK               0x00000001 /**< Transaction error */
0107
0108 /** Interrupt status bits for MAC interrupts
0109  *  These bits are associated with XTE_IPISR_OFFSET and XTE_IPIER_OFFSET
0110  *  registers.
0111  */
0112 #define XTE_IPXR_XMIT_DONE_MASK         0x00000001 /**< Tx complete */
0113 #define XTE_IPXR_RECV_DONE_MASK         0x00000002 /**< Rx complete */
0114 #define XTE_IPXR_AUTO_NEG_MASK          0x00000004 /**< Auto negotiation complete */
0115 #define XTE_IPXR_RECV_REJECT_MASK       0x00000008 /**< Rx packet rejected */
0116 #define XTE_IPXR_XMIT_SFIFO_EMPTY_MASK  0x00000010 /**< Tx status fifo empty */
0117 #define XTE_IPXR_RECV_LFIFO_EMPTY_MASK  0x00000020 /**< Rx length fifo empty */
0118 #define XTE_IPXR_XMIT_LFIFO_FULL_MASK   0x00000040 /**< Tx length fifo full */
0119 #define XTE_IPXR_RECV_LFIFO_OVER_MASK   0x00000080 /**< Rx length fifo overrun
0120                                                         Note that this signal is
0121                                                         no longer asserted by HW
0122                                                         */
0123 #define XTE_IPXR_RECV_LFIFO_UNDER_MASK  0x00000100 /**< Rx length fifo underrun */
0124 #define XTE_IPXR_XMIT_SFIFO_OVER_MASK   0x00000200 /**< Tx status fifo overrun */
0125 #define XTE_IPXR_XMIT_SFIFO_UNDER_MASK  0x00000400 /**< Tx status fifo underrun */
0126 #define XTE_IPXR_XMIT_LFIFO_OVER_MASK   0x00000800 /**< Tx length fifo overrun */
0127 #define XTE_IPXR_XMIT_LFIFO_UNDER_MASK  0x00001000 /**< Tx length fifo underrun */
0128 #define XTE_IPXR_RECV_PFIFO_ABORT_MASK  0x00002000 /**< Rx packet rejected due to
0129                                                         full packet FIFO */
0130 #define XTE_IPXR_RECV_LFIFO_ABORT_MASK  0x00004000 /**< Rx packet rejected due to
0131                                                         full length FIFO */
0132
0133 #define XTE_IPXR_RECV_DROPPED_MASK                                      \
0134     (XTE_IPXR_RECV_REJECT_MASK |                                        \
0135      XTE_IPXR_RECV_PFIFO_ABORT_MASK |                                   \
0136      XTE_IPXR_RECV_LFIFO_ABORT_MASK)    /**< IPXR bits that indicate a dropped
0137                                              receive frame */
0138 #define XTE_IPXR_XMIT_ERROR_MASK                                        \
0139     (XTE_IPXR_XMIT_SFIFO_OVER_MASK |                                    \
0140      XTE_IPXR_XMIT_SFIFO_UNDER_MASK |                                   \
0141      XTE_IPXR_XMIT_LFIFO_OVER_MASK |                                    \
0142      XTE_IPXR_XMIT_LFIFO_UNDER_MASK)    /**< IPXR bits that indicate transmit
0143                                              errors */
0144
0145 #define XTE_IPXR_RECV_ERROR_MASK                                        \
0146     (XTE_IPXR_RECV_DROPPED_MASK |                                       \
0147      XTE_IPXR_RECV_LFIFO_UNDER_MASK)    /**< IPXR bits that indicate receive
0148                                              errors */
0149
0150 #define XTE_IPXR_FIFO_FATAL_ERROR_MASK          \
0151     (XTE_IPXR_XMIT_SFIFO_OVER_MASK |            \
0152      XTE_IPXR_XMIT_SFIFO_UNDER_MASK |           \
0153      XTE_IPXR_XMIT_LFIFO_OVER_MASK |            \
0154      XTE_IPXR_XMIT_LFIFO_UNDER_MASK |           \
0155      XTE_IPXR_RECV_LFIFO_UNDER_MASK)    /**< IPXR bits that indicate errors with
0156                                              one of the length or status FIFOs
0157                                              that is fatal in nature. These bits
0158                                              can only be cleared by a device
0159                                              reset */
0160
0161 /** Software reset register (DSR)
0162  */
0163 #define XTE_DSR_RESET_MASK      0x0000000A  /**< Write this value to DSR to
0164                                                  reset entire core */
0165
0166
0167 /** Global interrupt enable register (DGIE)
0168  */
0169 #define XTE_DGIE_ENABLE_MASK    0x80000000  /**< Write this value to DGIE to
0170                                                  enable interrupts from this
0171                                                  device */
0172
0173 /** Control Register (CR)
0174  */
0175 #define XTE_CR_HTRST_MASK       0x00000008   /**< Reset hard temac */
0176 #define XTE_CR_BCREJ_MASK       0x00000004   /**< Disable broadcast address
0177                                                   filtering */
0178 #define XTE_CR_MCREJ_MASK       0x00000002   /**< Disable multicast address
0179                                                   filtering */
0180 #define XTE_CR_HDUPLEX_MASK     0x00000001   /**< Enable half duplex operation */
0181
0182
0183 /** Transmit Packet Length Register (TPLR)
0184  */
0185 #define XTE_TPLR_TXPL_MASK      0x00003FFF   /**< Tx packet length in bytes */
0186
0187
0188 /** Transmit Status Register (TSR)
0189  */
0190 #define XTE_TSR_TXED_MASK       0x80000000   /**< Excess deferral error */
0191 #define XTE_TSR_PFIFOU_MASK     0x40000000   /**< Packet FIFO underrun */
0192 #define XTE_TSR_TXA_MASK        0x3E000000   /**< Transmission attempts */
0193 #define XTE_TSR_TXLC_MASK       0x01000000   /**< Late collision error */
0194 #define XTE_TSR_TPCF_MASK       0x00000001   /**< Transmit packet complete
0195                                                   flag */
0196
0197 #define XTE_TSR_ERROR_MASK                 \
0198     (XTE_TSR_TXED_MASK |                   \
0199      XTE_TSR_PFIFOU_MASK |                 \
0200      XTE_TSR_TXLC_MASK)                      /**< TSR bits that indicate an
0201                                                   error */
0202
0203
0204 /** Receive Packet Length Register (RPLR)
0205  */
0206 #define XTE_RPLR_RXPL_MASK      0x00003FFF   /**< Rx packet length in bytes */
0207
0208
0209 /** Receive Status Register (RSR)
0210  */
0211 #define XTE_RSR_RPCF_MASK       0x00000001   /**< Receive packet complete
0212                                                   flag */
0213
0214 /** Interframe Gap Register (IFG)
0215  */
0216 #define XTE_IFG_IFGD_MASK       0x000000FF   /**< IFG delay */
0217
0218
0219 /** Transmit Pause Packet Register (TPPR)
0220  */
0221 #define XTE_TPPR_TPPD_MASK      0x0000FFFF   /**< Tx pause packet data */
0222
0223
0224 /** Receiver Configuration Word 1 (ERXC1)
0225  */
0226 #define XTE_ERXC1_RXRST_MASK    0x80000000   /**< Receiver reset */
0227 #define XTE_ERXC1_RXJMBO_MASK   0x40000000   /**< Jumbo frame enable */
0228 #define XTE_ERXC1_RXFCS_MASK    0x20000000   /**< FCS not stripped */
0229 #define XTE_ERXC1_RXEN_MASK     0x10000000   /**< Receiver enable */
0230 #define XTE_ERXC1_RXVLAN_MASK   0x08000000   /**< VLAN enable */
0231 #define XTE_ERXC1_RXHD_MASK     0x04000000   /**< Half duplex */
0232 #define XTE_ERXC1_RXLT_MASK     0x02000000   /**< Length/type check disable */
0233 #define XTE_ERXC1_ERXC1_MASK    0x0000FFFF   /**< Pause frame source address
0234                                                   bits [47:32]. Bits [31:0]
0235                                                   are stored in register
0236                                                   ERXC0 */
0237
0238
0239 /** Transmitter Configuration (ETXC)
0240  */
0241 #define XTE_ETXC_TXRST_MASK     0x80000000   /**< Transmitter reset */
0242 #define XTE_ETXC_TXJMBO_MASK    0x40000000   /**< Jumbo frame enable */
0243 #define XTE_ETXC_TXFCS_MASK     0x20000000   /**< Generate FCS */
0244 #define XTE_ETXC_TXEN_MASK      0x10000000   /**< Transmitter enable */
0245 #define XTE_ETXC_TXVLAN_MASK    0x08000000   /**< VLAN enable */
0246 #define XTE_ETXC_TXHD_MASK      0x04000000   /**< Half duplex */
0247 #define XTE_ETXC_TXIFG_MASK     0x02000000   /**< IFG adjust enable */
0248
0249
0250 /** Flow Control Configuration (EFCC)
0251  */
0252 #define XTE_EFCC_TXFLO_MASK     0x40000000   /**< Tx flow control enable */
0253 #define XTE_EFCC_RXFLO_MASK     0x20000000   /**< Rx flow control enable */
0254
0255
0256 /** EMAC Configuration (ECFG)
0257  */
0258 #define XTE_ECFG_LINKSPD_MASK   0xC0000000   /**< Link speed */
0259 #define XTE_ECFG_RGMII_MASK     0x20000000   /**< RGMII mode enable */
0260 #define XTE_ECFG_SGMII_MASK     0x10000000   /**< SGMII mode enable */
0261 #define XTE_ECFG_1000BASEX_MASK 0x08000000   /**< 1000BaseX mode enable */
0262 #define XTE_ECFG_HOSTEN_MASK    0x04000000   /**< Host interface enable */
0263 #define XTE_ECFG_TX16BIT        0x02000000   /**< 16 bit Tx client enable */
0264 #define XTE_ECFG_RX16BIT        0x01000000   /**< 16 bit Rx client enable */
0265
0266 #define XTE_ECFG_LINKSPD_10     0x00000000   /**< XTE_ECFG_LINKSPD_MASK for
0267                                                   10 Mbit */
0268 #define XTE_ECFG_LINKSPD_100    0x40000000   /**< XTE_ECFG_LINKSPD_MASK for
0269                                                   100 Mbit */
0270 #define XTE_ECFG_LINKSPD_1000   0x80000000   /**< XTE_ECFG_LINKSPD_MASK for
0271                                                   1000 Mbit */
0272
0273 /** EMAC RGMII/SGMII Configuration (EGMIC)
0274  */
0275 #define XTE_EGMIC_RGLINKSPD_MASK    0xC0000000   /**< RGMII link speed */
0276 #define XTE_EGMIC_SGLINKSPD_MASK    0x0000000C   /**< SGMII link speed */
0277 #define XTE_EGMIC_RGSTATUS_MASK     0x00000002   /**< RGMII link status */
0278 #define XTE_EGMIC_RGHALFDUPLEX_MASK 0x00000001   /**< RGMII half duplex */
0279
0280 #define XTE_EGMIC_RGLINKSPD_10      0x00000000   /**< XTE_EGMIC_RGLINKSPD_MASK
0281                                                       for 10 Mbit */
0282 #define XTE_EGMIC_RGLINKSPD_100     0x40000000   /**< XTE_EGMIC_RGLINKSPD_MASK
0283                                                       for 100 Mbit */
0284 #define XTE_EGMIC_RGLINKSPD_1000    0x80000000   /**< XTE_EGMIC_RGLINKSPD_MASK
0285                                                       for 1000 Mbit */
0286 #define XTE_EGMIC_SGLINKSPD_10      0x00000000   /**< XTE_SGMIC_RGLINKSPD_MASK
0287                                                       for 10 Mbit */
0288 #define XTE_EGMIC_SGLINKSPD_100     0x00000004   /**< XTE_SGMIC_RGLINKSPD_MASK
0289                                                       for 100 Mbit */
0290 #define XTE_EGMIC_SGLINKSPD_1000    0x00000008   /**< XTE_SGMIC_RGLINKSPD_MASK
0291                                                       for 1000 Mbit */
0292
0293 /** EMAC Management Configuration (EMC)
0294  */
0295 #define XTE_EMC_MDIO_MASK       0x00000040   /**< MII management enable */
0296 #define XTE_EMC_CLK_DVD_MAX     0x3F         /**< Maximum MDIO divisor */
0297
0298
0299 /** EMAC Unicast Address Register Word 1 (EUAW1)
0300  */
0301 #define XTE_EUAW1_MASK          0x0000FFFF   /**< Station address bits [47:32]
0302                                                   Station address bits [31:0]
0303                                                   are stored in register
0304                                                   EUAW0 */
0305
0306
0307 /** EMAC Multicast Address Register Word 1 (EMAW1)
0308  */
0309 #define XTE_EMAW1_CAMRNW_MASK   0x00800000   /**< CAM read/write control */
0310 #define XTE_EMAW1_CAMADDR_MASK  0x00030000   /**< CAM address mask */
0311 #define XTE_EUAW1_MASK          0x0000FFFF   /**< Multicast address bits [47:32]
0312                                                   Multicast address bits [31:0]
0313                                                   are stored in register
0314                                                   EMAW0 */
0315 #define XTE_EMAW1_CAMMADDR_SHIFT_MASK 16     /**< Number of bits to shift right
0316                                                   to align with
0317                                                   XTE_EMAW1_CAMADDR_MASK */
0318
0319
0320 /** EMAC Address Filter Mode (EAFM)
0321  */
0322 #define XTE_EAFM_EPPRM_MASK         0x80000000   /**< Promiscuous mode enable */
0323
0324
0325 /** EMAC MII Management Write Data (EMIID)
0326  */
0327 #define XTE_EMIID_MIIMWRDATA_MASK   0x0000FFFF   /**< Data port */
0328
0329
0330 /** EMAC MII Management Control (EMIIC)
0331  */
0332 #define XTE_EMIID_MIIMDECADDR_MASK  0x0000FFFF   /**< Address port */
0333
0334
0335 struct XilTemacStats
0336 {
0337   volatile uint32_t iInterrupts;
0338
0339   volatile uint32_t iRxInterrupts;
0340   volatile uint32_t iRxRejectedInterrupts;
0341   volatile uint32_t iRxRejectedInvalidFrame;
0342   volatile uint32_t iRxRejectedDataFifoFull;
0343   volatile uint32_t iRxRejectedLengthFifoFull;
0344   volatile uint32_t iRxMaxDrained;
0345   volatile uint32_t iRxStrayEvents;
0346
0347   volatile uint32_t iTxInterrupts;
0348   volatile uint32_t iTxMaxDrained;
0349 };
0350
0351 #define MAX_UNIT_BYTES 50
0352
0353 struct XilTemac
0354 {
0355   struct arpcom         iArpcom;
0356   struct XilTemacStats  iStats;
0357   struct ifnet*         iIfp;
0358
0359   char                  iUnitName[MAX_UNIT_BYTES];
0360
0361   uint32_t              iAddr;
0362   rtems_event_set       iIoEvent;
0363
0364   int                   iIsrVector;
0365
0366 #if PPC_HAS_CLASSIC_EXCEPTIONS
0367   rtems_isr_entry       iOldHandler;
0368 #else
0369   rtems_irq_connect_data iOldHandler;
0370 #endif
0371   int                   iIsPresent;
0372 };
0373
0374
0375 #endif /* _XILINX_EMAC_*/