include/bsp/opbintctrl.h

0001 /*  opbintctrl.h
0002  *
0003  *  This file contains definitions and declarations for the
0004  *  Xilinx Off Processor Bus (OPB) Interrupt Controller
0005  *
0006  *  Author: Keith Robertson <kjrobert@alumni.uwaterloo.ca>
0007  *  COPYRIGHT (c) 2005 by Linn Products Ltd, Scotland
0008  *
0009  *  The license and distribution terms for this file may be
0010  *  found in the file LICENSE in this distribution or at
0011  *  http://www.rtems.org/license/LICENSE.
0012  */
0013
0014 #ifndef _INCLUDE_OPBINTCTRL_H
0015 #define _INCLUDE_OPBINTCTRL_H
0016
0017 #include <rtems.h>
0018 #include <rtems/score/isr.h>
0019 #include <rtems/irq.h>
0020 #include <bspopts.h>
0021 #include RTEMS_XPARAMETERS_H
0022
0023 #define USE_GREG_INTERRUPTS
0024
0025 #ifdef __cplusplus
0026 extern "C" {
0027 #endif
0028
0029
0030 /* extern XIntc InterruptController;
0031  */
0032
0033
0034 /* Maximum number of IRQs.  Defined in vhdl model */
0035 #define OPB_INTC_IRQ_MAX      XPAR_INTC_MAX_NUM_INTR_INPUTS
0036
0037 /* Width of INTC registers.  Defined in vhdl model */
0038 #define OPB_INTC_REGISTER_WIDTH   32
0039
0040 /* Base Register address and register offsets.  Defined in vhdl model  */
0041 #define OPB_INTC_BASE         XPAR_INTC_SINGLE_BASEADDR
0042
0043
0044
0045
0046
0047 /* Interrupt Status Register */
0048 #define OPB_INTC_ISR        0x0
0049 /* Interrupt Pending Register (ISR && IER) */
0050 #define OPB_INTC_IPR        0x4
0051 /* Interrupt Enable Register */
0052 #define OPB_INTC_IER        0x8
0053 /* Interrupt Acknowledge Register */
0054 #define OPB_INTC_IAR        0xC
0055 /* Set Interrupt Enable (same as read/mask/write to IER) */
0056 #define OPB_INTC_SIE        0x10
0057 /* Clear Interrupt Enable (same as read/mask/write to IER) */
0058 #define OPB_INTC_CIE        0x14
0059 /* Interrupt Vector Address (highest priority vector number from IPR) */
0060 #define OPB_INTC_IVR        0x18
0061 /* Master Enable Register */
0062 #define OPB_INTC_MER        0x1C
0063
0064 /* Master Enable Register: Hardware Interrupt Enable */
0065 #define OPB_INTC_MER_HIE    0x2
0066
0067 /* Master Enable Register: Master IRQ Enable */
0068 #define OPB_INTC_MER_ME     0x1
0069
0070 #ifdef __cplusplus
0071 }
0072 #endif
0073
0074 #endif /*  _INCLUDE_OPBINTCTRL_H */