tqm8xx/start/mmutlbtab.c

0001 /*
0002  * RTEMS TQM8xx BSP
0003  *
0004  * This file contains the console driver.
0005  */
0006
0007 /*
0008  * Copyright (c) 1999, National Research Council of Canada
0009  * Copyright (c) 2008 Thomas Doerfler, embedded brains GmbH & Co. KG
0010  * All rights reserved.
0011  *
0012  * The license and distribution terms for this file may be
0013  * found in the file LICENSE in this distribution or at
0014  * http://www.rtems.org/license/LICENSE.
0015  */
0016
0017 #include <bsp.h>
0018 #include <mpc8xx/mmu.h>
0019 /*
0020  * This MMU_TLB_table is used to statically initialize the Table Lookaside
0021  * Buffers in the MMU of the TQM8xx board.
0022  *
0023  * We initialize the entries in both the instruction and data TLBs
0024  * with the same values - a few bits relevant to the data TLB are unused
0025  * in the instruction TLB.
0026  *
0027  * An Effective Page Number (EPN), Tablewalk Control Register (TWC) and
0028  * Real Page Number (RPN) value are supplied in the table for each TLB entry.
0029  *
0030  * The instruction and data TLBs each can hold 32 entries, so _TLB_Table must
0031  * not have more than 32 lines in it!
0032  *
0033  * We set up the virtual memory map so that virtual address of a
0034  * location is equal to its real address.
0035  */
0036 MMU_TLB_table_t MMU_TLB_table[] = {
0037   /*
0038    * DRAM: Start address 0x00000000, 128M,
0039    *    ASID=0x0, APG=0x0, not guarded memory, copyback data cache policy,
0040    *    R/W,X for all, no ASID comparison, not cache-inhibited.
0041    * EPN        TWC RPN
0042    */
0043   { 0x00000200, 0x0D,   0x000009FD },   /* DRAM - PS=8M */
0044   { 0x00800200, 0x0D,   0x008009FD },   /* DRAM - PS=8M */
0045   { 0x01000200, 0x0D,   0x010009FD },   /* DRAM - PS=8M */
0046   { 0x01800200, 0x0D,   0x018009FD },   /* DRAM - PS=8M */
0047   { 0x02000200, 0x0D,   0x020009FD },   /* DRAM - PS=8M */
0048   { 0x02800200, 0x0D,   0x028009FD },   /* DRAM - PS=8M */
0049   { 0x03000200, 0x0D,   0x030009FD },   /* DRAM - PS=8M */
0050   { 0x03800200, 0x0D,   0x038009FD },   /* DRAM - PS=8M */
0051   { 0x04000200, 0x0D,   0x040009FD },   /* DRAM - PS=8M */
0052   { 0x04800200, 0x0D,   0x048009FD },   /* DRAM - PS=8M */
0053   { 0x05000200, 0x0D,   0x050009FD },   /* DRAM - PS=8M */
0054   { 0x05800200, 0x0D,   0x058009FD },   /* DRAM - PS=8M */
0055   { 0x06000200, 0x0D,   0x060009FD },   /* DRAM - PS=8M */
0056   { 0x06800200, 0x0D,   0x068009FD },   /* DRAM - PS=8M */
0057   { 0x07000200, 0x0D,   0x070009FD },   /* DRAM - PS=8M */
0058   { 0x07800200, 0x0D,   0x078009FD },   /* DRAM - PS=8M */
0059   /*
0060    *
0061    * (IMMR-SPRs) Dual Port RAM: Start address 0xFA200000, 16K,
0062    *    ASID=0x0, APG=0x0, guarded memory, write-through data cache policy,
0063    *    R/W,X for all, no ASID comparison, cache-inhibited.
0064    *
0065    *    Note: We use the value in MBXA/PG2, which is also the value that
0066    *    EPPC-Bug programmed into our boards. The alternative is the value
0067    *    in MBXA/PG1: 0xFFA00000. This value might well depend on the revision
0068    *    of the firmware.
0069    * EPN        TWC RPN
0070    */
0071   { 0xFA200200, 0x13,   0xFA2009FF },   /* IMMR - PS=16K */
0072   /*
0073    *
0074    * Flash: Start address 0x40000000, 8M,
0075    *    ASID=0x0, APG=0x0, not guarded memory,
0076    *    R/O,X for all, no ASID comparison, not cache-inhibited.
0077    * EPN        TWC RPN
0078    */
0079   { 0x40000200, 0x0D,   0x40000CFD }    /* Flash - PS=8M   */
0080 };
0081
0082 /*
0083  * MMU_N_TLB_Table_Entries is defined here because the size of the
0084  * MMU_TLB_table is only known in this file.
0085  */
0086 int MMU_N_TLB_Table_Entries = ( sizeof(MMU_TLB_table) / sizeof(MMU_TLB_table[0]) );