tqm8xx/start/mmu.c

0001 /*
0002  * mmu.c
0003  *
0004  * This file contains routines for initializing
0005  * and manipulating the MMU on the MPC8xx.
0006  *
0007  * Copyright (c) 1999, National Research Council of Canada
0008  *
0009  * The license and distribution terms for this file may be
0010  * found in the file LICENSE in this distribution or at
0011  * http://www.rtems.org/license/LICENSE.
0012  */
0013
0014 #include <rtems.h>
0015 #include <rtems/powerpc/powerpc.h>
0016
0017 #include <mpc8xx.h>
0018 #include <mpc8xx/mmu.h>
0019
0020 /*
0021  * mmu_init
0022  *
0023  * This routine sets up the virtual memory maps on an MPC8xx.
0024  * The MPC8xx does not support block address translation (BATs)
0025  * and does not have segment registers. Thus, we must set up page
0026  * translation. However, its MMU supports variable size pages
0027  * (1-, 4-, 16-, 512-Kbyte or 8-Mbyte), which simplifies the task.
0028  *
0029  * The MPC8xx has separate data and instruction 32-entry translation
0030  * lookaside buffers (TLB). By mapping all of DRAM as one huge page,
0031  * we can preload the TLBs and not have to be concerned with taking
0032  * TLB miss exceptions.
0033  *
0034  * We set up the virtual memory map so that virtual address of a
0035  * location is equal to its real address.
0036  */
0037 void mmu_init( void )
0038 {
0039   register uint32_t   reg1, i;
0040
0041   /*
0042    * Initialize the TLBs
0043    *
0044    * Instruction address translation and data address translation
0045    * must be disabled during initialization (IR=0, DR=0 in MSR).
0046    * We can assume the MSR has already been set this way.
0047    */
0048
0049   /*
0050    * Initialize IMMU & DMMU Control Registers (MI_CTR & MD_CTR)
0051    *    GPM [0]         0b0 = PowerPC mode
0052    *    PPM [1]         0b0 = Page resolution of protection
0053    *    CIDEF [2]       0b0/0b0 = Default cache-inhibit attribute =
0054    *                            NO for IMMU, NO for DMMU
0055    *                            NOTE: it is vital that data caching is ON, when
0056    *                            DMMU is off, otherwise valid/dirty values in
0057    *                            cache would be ignored during exception entry
0058    *    reserved/WTDEF [3]  0b0 = Default write-through attribute = not
0059    *    RSV4x [4]       0b0 = 4 entries not reserved
0060    *    reserved/TWAM [5]   0b0/0b1 = 4-Kbyte page hardware assist
0061    *    PPCS [6]        0b0 = Ignore user/supervisor state
0062    *    reserved [7-18]     0x00
0063    *    xTLB_INDX [19-23]   31 = 0x1F
0064    *    reserved [24-31]    0x00
0065    *
0066    * Note: It is important that cache-inhibit be set as the default for the
0067    * data cache when the DMMU is disabled in order to prevent internal memory
0068    * mapped registers from being cached accidentally when address translation
0069    * is turned off at the start of exception processing.
0070    */
0071   reg1 = M8xx_MI_CTR_ITLB_INDX(31);
0072   _mtspr( M8xx_MI_CTR, reg1 );
0073   reg1 = M8xx_MD_CTR_TWAM | M8xx_MD_CTR_DTLB_INDX(31);
0074   _mtspr( M8xx_MD_CTR, reg1 );
0075   _isync;
0076
0077   /*
0078    * Invalidate all TLB entries in both TLBs.
0079    * Note: We rely on the RSV4 bit in MI_CTR and MD_CTR being 0b0, so
0080    *       all 32 entries are invalidated.
0081    */
0082   __asm__ volatile ("tlbia\n"::);
0083   _isync;
0084
0085   /*
0086    * Set Current Address Space ID Register (M_CASID).
0087    * Supervisor: CASID = 0
0088    */
0089   reg1 = 0;
0090   _mtspr( M8xx_M_CASID, reg1 );
0091
0092   /*
0093    * Initialize the MMU Access Protection Registers (MI_AP, MD_AP)
0094    * We ignore the Access Protection Group (APG) mechanism globally
0095    * by setting all of the Mx_AP fields to 0b01 : client access
0096    * permission is defined by page protection bits.
0097    */
0098   reg1 = 0x55555555;
0099   _mtspr( M8xx_MI_AP, reg1 );
0100   _mtspr( M8xx_MD_AP, reg1 );
0101
0102   /*
0103    * Load both 32-entry TLBs with values from the MMU_TLB_table
0104    * which is defined in the BSP.
0105    * Note the _TLB_Table must have at most 32 entries. This code
0106    * makes no effort to enforce this restriction.
0107    */
0108   for( i = 0; i < MMU_N_TLB_Table_Entries; ++i ) {
0109     reg1 = MMU_TLB_table[i].mmu_epn;
0110     _mtspr( M8xx_MI_EPN, reg1 );
0111     _mtspr( M8xx_MD_EPN, reg1 );
0112     reg1 = MMU_TLB_table[i].mmu_twc;
0113     _mtspr( M8xx_MI_TWC, reg1 );
0114     _mtspr( M8xx_MD_TWC, reg1 );
0115     reg1 = MMU_TLB_table[i].mmu_rpn;    /* RPN must be written last! */
0116     _mtspr( M8xx_MI_RPN, reg1 );
0117     _mtspr( M8xx_MD_RPN, reg1 );
0118   }
0119
0120   /*
0121    * Turn on address translation by setting MSR[IR] and MSR[DR].
0122    */
0123   _CPU_MSR_GET( reg1 );
0124   reg1 |= PPC_MSR_IR | PPC_MSR_DR;
0125   _CPU_MSR_SET( reg1 );
0126 }