tqm8xx/start/cpuinit.c

0001 /*
0002  *  cpuinit.c
0003  *
0004  *  TQM8xx initialization routines.
0005  * derived from MBX8xx BSP
0006  * adapted to TQM8xx by Thomas Doerfler <Thomas.Doerfler@embedded-brains.de>
0007  *
0008  *  Copyright (c) 1999, National Research Council of Canada
0009  *
0010  *  The license and distribution terms for this file may be
0011  *  found in the file LICENSE in this distribution or at
0012  *  http://www.rtems.org/license/LICENSE.
0013  */
0014
0015 #include <bsp.h>
0016 #include <bsp/tqm.h>
0017
0018
0019 /*
0020  *  Initialize TQM8xx
0021  */
0022 void _InitTQM8xx (void)
0023 {
0024   register uint32_t   r1;
0025
0026   /*
0027    * Initialize the Instruction Support Control Register (ICTRL) to a
0028    * an appropriate value for normal operation. A different value,
0029    * such as 0x0, may be more appropriate for debugging.
0030    */
0031   r1 = 0x00000007;
0032   _mtspr( M8xx_ICTRL, r1 );
0033
0034   /*
0035    * Disable and invalidate the instruction and data caches.
0036    */
0037   r1 = M8xx_CACHE_CMD_DISABLE;
0038   _mtspr( M8xx_IC_CST, r1 );
0039   _isync;
0040   r1 = M8xx_CACHE_CMD_UNLOCKALL;
0041   _mtspr( M8xx_IC_CST, r1 );
0042   _isync;
0043   r1 = M8xx_CACHE_CMD_INVALIDATE;   /* invalidate all */
0044   _mtspr( M8xx_IC_CST, r1 );
0045   _isync;
0046
0047   r1 = M8xx_CACHE_CMD_DISABLE;
0048   _mtspr( M8xx_DC_CST, r1 );
0049   _isync;
0050   r1 = M8xx_CACHE_CMD_UNLOCKALL;
0051   _mtspr( M8xx_DC_CST, r1 );
0052   _isync;
0053   r1 = M8xx_CACHE_CMD_INVALIDATE;   /* invalidate all */
0054   _mtspr( M8xx_DC_CST, r1 );
0055   _isync;
0056
0057   /*
0058    * Initialize the SIU Module Configuration Register (SIUMCR)
0059    * m8xx.siumcr = 0x00602900, the default value.
0060    */
0061   m8xx.siumcr = M8xx_SIUMCR_EARP0 | M8xx_SIUMCR_DBGC3 | M8xx_SIUMCR_DBPC0 |
0062         M8xx_SIUMCR_DPC | M8xx_SIUMCR_MLRC2 | M8xx_SIUMCR_SEME;
0063
0064   /*
0065    * Initialize the System Protection Control Register (SYPCR).
0066    * The SYPCR can only be written once after Reset.
0067    *    - Enable bus monitor
0068    *    - Disable software watchdog timer
0069    * m8xx.sypcr = 0xFFFFFF88, the default MBX and firmware value.
0070    */
0071   m8xx.sypcr = M8xx_SYPCR_SWTC(0xFFFF) | M8xx_SYPCR_BMT(0xFF) |
0072         M8xx_SYPCR_BME | M8xx_SYPCR_SWF;
0073
0074   /* Initialize the SIU Interrupt Edge Level Mask Register (SIEL) */
0075   m8xx.siel = 0xAAAA0000;           /* Default MBX and firmware value. */
0076
0077   /* Initialize the Transfer Error Status Register (TESR) */
0078   m8xx.tesr = 0xFFFFFFFF;           /* Default firmware value. */
0079
0080   /* Initialize the SDMA Configuration Register (SDCR) */
0081   m8xx.sdcr = 0x00000001;           /* Default firmware value. */
0082
0083   /*
0084    * Initialize the Timebase Status and Control Register (TBSCR)
0085    * m8xx.tbscr = 0x00C3, default MBX and firmware value.
0086    */
0087   m8xx.tbscrk = M8xx_UNLOCK_KEY;    /* unlock TBSCR */
0088   m8xx.tbscr = M8xx_TBSCR_REFA | M8xx_TBSCR_REFB |
0089         M8xx_TBSCR_TBF | M8xx_TBSCR_TBE;
0090
0091   /* Initialize the Real-Time Clock Status and Control Register (RTCSC) */
0092   m8xx.rtcsk = M8xx_UNLOCK_KEY;     /* unlock RTCSC */
0093   m8xx.rtcsc = 0x00C3;          /* Default MBX and firmware value. */
0094
0095   /* Unlock other Real-Time Clock registers */
0096   m8xx.rtck = M8xx_UNLOCK_KEY;      /* unlock RTC */
0097   m8xx.rtseck = M8xx_UNLOCK_KEY;    /* unlock RTSEC */
0098   m8xx.rtcalk = M8xx_UNLOCK_KEY;    /* unlock RTCAL */
0099
0100   /* Initialize the Periodic Interrupt Status and Control Register (PISCR) */
0101   m8xx.piscrk = M8xx_UNLOCK_KEY;    /* unlock PISCR */
0102   m8xx.piscr = 0x0083;          /* Default MBX and firmware value. */
0103
0104   /* Initialize the System Clock and Reset Control Register (SCCR)
0105    * Set the clock sources and division factors:
0106    *   Timebase Source is GCLK2 / 16
0107    */
0108   m8xx.sccrk = M8xx_UNLOCK_KEY;     /* unlock SCCR */
0109   m8xx.sccr |= 0x02000000;
0110
0111   /* Unlock the timebase and decrementer registers. */
0112   m8xx.tbk = M8xx_UNLOCK_KEY;
0113   /*
0114    * Initialize decrementer register to a large value to
0115    * guarantee that a decrementer interrupt will not be
0116    * generated before the kernel is fully initialized.
0117    */
0118   r1 = 0x7FFFFFFF;
0119   _mtspr( M8xx_DEC, r1 );
0120
0121   /* Initialize the timebase register (TB is 64 bits) */
0122   r1 = 0x00000000;
0123   _mtspr( M8xx_TBU_WR, r1 );
0124   _mtspr( M8xx_TBL_WR, r1 );
0125 }
0126 /*
0127  * further initialization (called from bsp_start)
0128  */
0129 void cpu_init(void)
0130 {
0131   /* mmu initialization */
0132   mmu_init();
0133 }