include/bsp/irq.h

0001 /* SPDX-License-Identifier: BSD-2-Clause */
0002
0003 /*
0004  * RTEMS TQM8xx BSP
0005  *
0006  * This file contains the console driver.
0007  *
0008  * Derived from: generic MPC83xx BSP
0009  */
0010
0011 /*
0012  * Copyright (c) 2008 Thomas Doerfler, embedded brains GmbH & Co. KG
0013  * All rights reserved.
0014  *
0015  * Redistribution and use in source and binary forms, with or without
0016  * modification, are permitted provided that the following conditions
0017  * are met:
0018  * 1. Redistributions of source code must retain the above copyright
0019  *    notice, this list of conditions and the following disclaimer.
0020  * 2. Redistributions in binary form must reproduce the above copyright
0021  *    notice, this list of conditions and the following disclaimer in the
0022  *    documentation and/or other materials provided with the distribution.
0023  *
0024  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
0025  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
0026  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
0027  * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
0028  * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
0029  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
0030  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
0031  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
0032  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
0033  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
0034  * POSSIBILITY OF SUCH DAMAGE.
0035  */
0036
0037 #ifndef TQM8xx_IRQ_IRQ_H
0038 #define TQM8xx_IRQ_IRQ_H
0039
0040 #include <stdbool.h>
0041
0042 #include <rtems.h>
0043 #include <rtems/irq.h>
0044 #include <rtems/irq-extension.h>
0045
0046 /*
0047  * the following definitions specify the indices used
0048  * to interface the interrupt handler API
0049  */
0050
0051 /*
0052  * Peripheral IRQ handlers related definitions
0053  */
0054 #define BSP_SIU_PER_IRQ_NUMBER   16
0055 #define BSP_SIU_IRQ_LOWEST_OFFSET 0
0056 #define BSP_SIU_IRQ_MAX_OFFSET   (BSP_SIU_IRQ_LOWEST_OFFSET\
0057                                   +BSP_SIU_PER_IRQ_NUMBER-1)
0058
0059 #define BSP_IS_SIU_IRQ(irqnum)              \
0060           (((irqnum) >= BSP_SIU_IRQ_LOWEST_OFFSET) &&   \
0061        ((irqnum) <= BSP_SIU_IRQ_MAX_OFFSET))
0062
0063 #define BSP_CPM_PER_IRQ_NUMBER   32
0064 #define BSP_CPM_IRQ_LOWEST_OFFSET (BSP_SIU_IRQ_MAX_OFFSET+1)
0065 #define BSP_CPM_IRQ_MAX_OFFSET   (BSP_CPM_IRQ_LOWEST_OFFSET\
0066                                   +BSP_CPM_PER_IRQ_NUMBER-1)
0067
0068 #define BSP_IS_CPM_IRQ(irqnum)              \
0069           (((irqnum) >= BSP_CPM_IRQ_LOWEST_OFFSET) &&   \
0070        ((irqnum) <= BSP_CPM_IRQ_MAX_OFFSET))
0071 /*
0072  * Processor IRQ handlers related definitions
0073  */
0074 #define BSP_PROCESSOR_IRQ_NUMBER        1
0075 #define BSP_PROCESSOR_IRQ_LOWEST_OFFSET (BSP_CPM_IRQ_MAX_OFFSET+1)
0076 #define BSP_PROCESSOR_IRQ_MAX_OFFSET    (BSP_PROCESSOR_IRQ_LOWEST_OFFSET\
0077                                          +BSP_PROCESSOR_IRQ_NUMBER-1)
0078
0079 #define BSP_IS_PROCESSOR_IRQ(irqnum)                \
0080           (((irqnum) >= BSP_PROCESSOR_IRQ_LOWEST_OFFSET) && \
0081        ((irqnum) <= BSP_PROCESSOR_IRQ_MAX_OFFSET))
0082 /*
0083  * Summary
0084  */
0085 #define BSP_IRQ_NUMBER                  (BSP_PROCESSOR_IRQ_MAX_OFFSET+1)
0086 #define BSP_LOWEST_OFFSET       BSP_SIU_IRQ_LOWEST_OFFSET
0087 #define BSP_MAX_OFFSET                  BSP_PROCESSOR_IRQ_MAX_OFFSET
0088
0089 #define BSP_IS_VALID_IRQ(irqnum)    \
0090           (BSP_IS_PROCESSOR_IRQ(irqnum) \
0091            || BSP_IS_SIU_IRQ(irqnum)    \
0092            || BSP_IS_CPM_IRQ(irqnum))
0093
0094 #ifndef ASM
0095 #ifdef __cplusplus
0096 extern "C" {
0097 #endif
0098
0099 /*
0100  * index table for the module specific handlers, a few entries are only placeholders
0101  */
0102   typedef enum {
0103     BSP_SIU_EXT_IRQ_0       = BSP_SIU_IRQ_LOWEST_OFFSET + 0,
0104     BSP_SIU_INT_IRQ_0       = BSP_SIU_IRQ_LOWEST_OFFSET + 1,
0105     BSP_SIU_EXT_IRQ_1       = BSP_SIU_IRQ_LOWEST_OFFSET + 2,
0106     BSP_SIU_INT_IRQ_1       = BSP_SIU_IRQ_LOWEST_OFFSET + 3,
0107     BSP_SIU_EXT_IRQ_2       = BSP_SIU_IRQ_LOWEST_OFFSET + 4,
0108     BSP_SIU_INT_IRQ_2       = BSP_SIU_IRQ_LOWEST_OFFSET + 5,
0109     BSP_SIU_EXT_IRQ_3       = BSP_SIU_IRQ_LOWEST_OFFSET + 6,
0110     BSP_SIU_INT_IRQ_3       = BSP_SIU_IRQ_LOWEST_OFFSET + 7,
0111     BSP_SIU_EXT_IRQ_4       = BSP_SIU_IRQ_LOWEST_OFFSET + 8,
0112     BSP_SIU_INT_IRQ_4       = BSP_SIU_IRQ_LOWEST_OFFSET + 9,
0113     BSP_SIU_EXT_IRQ_5       = BSP_SIU_IRQ_LOWEST_OFFSET + 10,
0114     BSP_SIU_INT_IRQ_5       = BSP_SIU_IRQ_LOWEST_OFFSET + 11,
0115     BSP_SIU_EXT_IRQ_6       = BSP_SIU_IRQ_LOWEST_OFFSET + 12,
0116     BSP_SIU_INT_IRQ_6       = BSP_SIU_IRQ_LOWEST_OFFSET + 13,
0117     BSP_SIU_EXT_IRQ_7       = BSP_SIU_IRQ_LOWEST_OFFSET + 14,
0118     BSP_SIU_INT_IRQ_7       = BSP_SIU_IRQ_LOWEST_OFFSET + 15,
0119     BSP_SIU_IRQ_LAST        = BSP_SIU_IRQ_MAX_OFFSET,
0120   /*
0121      * Some CPM IRQ symbolic name definition
0122      */
0123     BSP_CPM_IRQ_ERROR       = (BSP_CPM_IRQ_LOWEST_OFFSET),
0124     BSP_CPM_IRQ_PARALLEL_IO_PC4 = (BSP_CPM_IRQ_LOWEST_OFFSET + 1),
0125     BSP_CPM_IRQ_PARALLEL_IO_PC5 = (BSP_CPM_IRQ_LOWEST_OFFSET + 2),
0126     BSP_CPM_IRQ_SMC2_OR_PIP = (BSP_CPM_IRQ_LOWEST_OFFSET + 3),
0127     BSP_CPM_IRQ_SMC1        = (BSP_CPM_IRQ_LOWEST_OFFSET + 4),
0128     BSP_CPM_IRQ_SPI     = (BSP_CPM_IRQ_LOWEST_OFFSET + 5),
0129     BSP_CPM_IRQ_PARALLEL_IO_PC6 = (BSP_CPM_IRQ_LOWEST_OFFSET + 6),
0130     BSP_CPM_IRQ_TIMER_4     = (BSP_CPM_IRQ_LOWEST_OFFSET + 7),
0131     BSP_CPM_IRQ_PARALLEL_IO_PC7 = (BSP_CPM_IRQ_LOWEST_OFFSET + 9),
0132     BSP_CPM_IRQ_PARALLEL_IO_PC8 = (BSP_CPM_IRQ_LOWEST_OFFSET + 10),
0133     BSP_CPM_IRQ_PARALLEL_IO_PC9 = (BSP_CPM_IRQ_LOWEST_OFFSET + 11),
0134     BSP_CPM_IRQ_TIMER_3     = (BSP_CPM_IRQ_LOWEST_OFFSET + 12),
0135     BSP_CPM_IRQ_PARALLEL_IO_PC10= (BSP_CPM_IRQ_LOWEST_OFFSET + 14),
0136     BSP_CPM_IRQ_PARALLEL_IO_PC11= (BSP_CPM_IRQ_LOWEST_OFFSET + 15),
0137     BSP_CPM_I2C         = (BSP_CPM_IRQ_LOWEST_OFFSET + 16),
0138     BSP_CPM_RISC_TIMER_TABLE    = (BSP_CPM_IRQ_LOWEST_OFFSET + 17),
0139     BSP_CPM_IRQ_TIMER_2     = (BSP_CPM_IRQ_LOWEST_OFFSET + 18),
0140     BSP_CPM_IDMA2       = (BSP_CPM_IRQ_LOWEST_OFFSET + 20),
0141     BSP_CPM_IDMA1       = (BSP_CPM_IRQ_LOWEST_OFFSET + 21),
0142     BSP_CPM_SDMA_CHANNEL_BUS_ERR= (BSP_CPM_IRQ_LOWEST_OFFSET + 22),
0143     BSP_CPM_IRQ_PARALLEL_IO_PC12= (BSP_CPM_IRQ_LOWEST_OFFSET + 23),
0144     BSP_CPM_IRQ_PARALLEL_IO_PC13= (BSP_CPM_IRQ_LOWEST_OFFSET + 24),
0145     BSP_CPM_IRQ_TIMER_1     = (BSP_CPM_IRQ_LOWEST_OFFSET + 25),
0146     BSP_CPM_IRQ_PARALLEL_IO_PC14= (BSP_CPM_IRQ_LOWEST_OFFSET + 26),
0147     BSP_CPM_IRQ_SCC4        = (BSP_CPM_IRQ_LOWEST_OFFSET + 27),
0148     BSP_CPM_IRQ_SCC3        = (BSP_CPM_IRQ_LOWEST_OFFSET + 28),
0149     BSP_CPM_IRQ_SCC2        = (BSP_CPM_IRQ_LOWEST_OFFSET + 29),
0150     BSP_CPM_IRQ_SCC1        = (BSP_CPM_IRQ_LOWEST_OFFSET + 30),
0151     BSP_CPM_IRQ_PARALLEL_IO_PC15= (BSP_CPM_IRQ_LOWEST_OFFSET + 31),
0152     BSP_CPM_IRQ_LAST     = BSP_CPM_IRQ_MAX_OFFSET,
0153   } rtems_irq_symbolic_name;
0154
0155   /*
0156    * Symbolic name for CPM interrupt on SIU Internal level 2
0157    */
0158 #define BSP_CPM_INTERRUPT   BSP_SIU_INT_IRQ_2
0159 #define BSP_PERIODIC_TIMER  BSP_SIU_INT_IRQ_6
0160 #define BSP_FAST_ETHERNET_CTRL  BSP_SIU_INT_IRQ_3
0161
0162 #define BSP_INTERRUPT_VECTOR_COUNT (BSP_MAX_OFFSET + 1)
0163
0164 extern int BSP_irq_enabled_at_cpm(const rtems_irq_number irqLine);
0165
0166 #ifdef __cplusplus
0167 }
0168 #endif
0169 #endif /* ASM */
0170
0171 #endif /* TQM8XX_IRQ_IRQ_H */