t32mppc/start/start.S

0001 /* SPDX-License-Identifier: BSD-2-Clause */
0002
0003 /*
0004  * Copyright (C) 2012, 2017 embedded brains GmbH & Co. KG
0005  *
0006  * Redistribution and use in source and binary forms, with or without
0007  * modification, are permitted provided that the following conditions
0008  * are met:
0009  * 1. Redistributions of source code must retain the above copyright
0010  *    notice, this list of conditions and the following disclaimer.
0011  * 2. Redistributions in binary form must reproduce the above copyright
0012  *    notice, this list of conditions and the following disclaimer in the
0013  *    documentation and/or other materials provided with the distribution.
0014  *
0015  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
0016  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
0017  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
0018  * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
0019  * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
0020  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
0021  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
0022  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
0023  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
0024  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
0025  * POSSIBILITY OF SUCH DAMAGE.
0026  */
0027
0028 #include <bspopts.h>
0029
0030 #include <rtems/score/percpu.h>
0031 #include <libcpu/powerpc-utility.h>
0032 #include <bsp/vectors.h>
0033
0034     .globl _start
0035     .globl bsp_exc_vector_base
0036
0037     .section ".bsp_start_text", "ax"
0038
0039     /* Primitive NULL pointer protection */
0040 .rept 1024
0041     sc
0042 .endr
0043
0044 _start:
0045     /* Enable time base */
0046     li  r0, 0x4000
0047     mtspr   HID0, r0
0048
0049     /* Initialize start stack */
0050     LA  r1, _ISR_Stack_area_end
0051     subi    r1, r1, 16
0052     li  r0, 0
0053     stw r0, 0(r1)
0054
0055     SET_SELF_CPU_CONTROL    r3, r4
0056
0057     /* Copy fast text */
0058     LWI r3, bsp_section_fast_text_begin
0059     LWI r4, bsp_section_fast_text_load_begin
0060     LWI r5, bsp_section_fast_text_size
0061     bl  copy
0062
0063     /* Copy read-only data */
0064     LWI r3, bsp_section_rodata_begin
0065     LWI r4, bsp_section_rodata_load_begin
0066     LWI r5, bsp_section_rodata_size
0067     bl  copy
0068
0069     /* Copy fast data */
0070     LWI r3, bsp_section_fast_data_begin
0071     LWI r4, bsp_section_fast_data_load_begin
0072     LWI r5, bsp_section_fast_data_size
0073     bl  copy
0074
0075     /* Copy data */
0076     LWI r3, bsp_section_data_begin
0077     LWI r4, bsp_section_data_load_begin
0078     LWI r5, bsp_section_data_size
0079     bl  copy
0080
0081     /* Clear SBSS */
0082     LWI r3, bsp_section_sbss_begin
0083     LWI r4, bsp_section_sbss_size
0084     bl  bsp_start_zero
0085
0086     /* Clear BSS */
0087     LWI r3, bsp_section_bss_begin
0088     LWI r4, bsp_section_bss_size
0089     bl  bsp_start_zero
0090
0091     /* Set up EABI and SYSV environment */
0092     bl  __eabi
0093
0094     /* Clear command line */
0095     li  r3, 0
0096
0097     bl  boot_card
0098
0099 twiddle:
0100     b   twiddle
0101
0102 copy:
0103     cmpw    r3, r4
0104     beqlr
0105     b   memcpy
0106
0107     /* Exception vector prologues area */
0108     .section ".bsp_start_text", "ax"
0109     .align 4
0110 bsp_exc_vector_base:
0111     /* Critical input */
0112     PPC_REG_STORE_UPDATE    r1, -EXC_GENERIC_SIZE(r1)
0113     PPC_REG_STORE   r3, GPR3_OFFSET(r1)
0114     li  r3, 0
0115     b   ppc_exc_fatal_critical
0116     /* Machine check */
0117     PPC_REG_STORE_UPDATE    r1, -EXC_GENERIC_SIZE(r1)
0118     PPC_REG_STORE   r3, GPR3_OFFSET(r1)
0119     li  r3, 1
0120     b   ppc_exc_fatal_machine_check
0121     /* Data storage */
0122     PPC_REG_STORE_UPDATE    r1, -EXC_GENERIC_SIZE(r1)
0123     PPC_REG_STORE   r3, GPR3_OFFSET(r1)
0124     li  r3, 2
0125     b   ppc_exc_fatal_normal
0126     /* Instruction storage */
0127     PPC_REG_STORE_UPDATE    r1, -EXC_GENERIC_SIZE(r1)
0128     PPC_REG_STORE   r3, GPR3_OFFSET(r1)
0129     li  r3, 3
0130     b   ppc_exc_fatal_normal
0131     /* External input */
0132     PPC_REG_STORE_UPDATE    r1, -PPC_EXC_INTERRUPT_FRAME_SIZE(r1)
0133     PPC_REG_STORE   r3, GPR3_OFFSET(r1)
0134     li  r3, 4
0135     b   ppc_exc_interrupt
0136     /* Alignment */
0137     PPC_REG_STORE_UPDATE    r1, -EXC_GENERIC_SIZE(r1)
0138     PPC_REG_STORE   r3, GPR3_OFFSET(r1)
0139     li  r3, 5
0140     b   ppc_exc_fatal_normal
0141     /* Program */
0142     PPC_REG_STORE_UPDATE    r1, -EXC_GENERIC_SIZE(r1)
0143     PPC_REG_STORE   r3, GPR3_OFFSET(r1)
0144     li  r3, 6
0145     b   ppc_exc_fatal_normal
0146     /* Floating-point unavailable */
0147     PPC_REG_STORE_UPDATE    r1, -EXC_GENERIC_SIZE(r1)
0148     PPC_REG_STORE   r3, GPR3_OFFSET(r1)
0149     li  r3, 7
0150     b   ppc_exc_fatal_normal
0151     /* System call */
0152     PPC_REG_STORE_UPDATE    r1, -EXC_GENERIC_SIZE(r1)
0153     PPC_REG_STORE   r3, GPR3_OFFSET(r1)
0154     li  r3, 8
0155     b   ppc_exc_fatal_normal
0156     /* APU unavailable */
0157     PPC_REG_STORE_UPDATE    r1, -EXC_GENERIC_SIZE(r1)
0158     PPC_REG_STORE   r3, GPR3_OFFSET(r1)
0159     li  r3, 9
0160     b   ppc_exc_fatal_normal
0161     /* Decrementer */
0162     PPC_REG_STORE_UPDATE    r1, -PPC_EXC_INTERRUPT_FRAME_SIZE(r1)
0163     PPC_REG_STORE   r3, PPC_EXC_GPR3_PROLOGUE_OFFSET(r1)
0164     li  r3, 10
0165     b   ppc_exc_interrupt
0166     /* Fixed-interval timer interrupt */
0167     PPC_REG_STORE_UPDATE    r1, -EXC_GENERIC_SIZE(r1)
0168     PPC_REG_STORE   r3, GPR3_OFFSET(r1)
0169     li  r3, 11
0170     b   ppc_exc_fatal_normal
0171     /* Watchdog timer interrupt */
0172     PPC_REG_STORE_UPDATE    r1, -EXC_GENERIC_SIZE(r1)
0173     PPC_REG_STORE   r3, GPR3_OFFSET(r1)
0174     li  r3, 12
0175     b   ppc_exc_fatal_critical
0176     /* Data TLB error */
0177     PPC_REG_STORE_UPDATE    r1, -EXC_GENERIC_SIZE(r1)
0178     PPC_REG_STORE   r3, GPR3_OFFSET(r1)
0179     li  r3, 13
0180     b   ppc_exc_fatal_normal
0181     /* Instruction TLB error */
0182     PPC_REG_STORE_UPDATE    r1, -EXC_GENERIC_SIZE(r1)
0183     PPC_REG_STORE   r3, GPR3_OFFSET(r1)
0184     li  r3, 14
0185     b   ppc_exc_fatal_normal
0186     /* Debug */
0187     PPC_REG_STORE_UPDATE    r1, -EXC_GENERIC_SIZE(r1)
0188     PPC_REG_STORE   r3, GPR3_OFFSET(r1)
0189     li  r3, 15
0190     b   ppc_exc_fatal_debug
0191     /* SPE APU unavailable or AltiVec unavailable */
0192     PPC_REG_STORE_UPDATE    r1, -EXC_GENERIC_SIZE(r1)
0193     PPC_REG_STORE   r3, GPR3_OFFSET(r1)
0194     li  r3, 32
0195     b   ppc_exc_fatal_normal
0196     /* SPE floating-point data exception or AltiVec assist */
0197     PPC_REG_STORE_UPDATE    r1, -EXC_GENERIC_SIZE(r1)
0198     PPC_REG_STORE   r3, GPR3_OFFSET(r1)
0199     li  r3, 33
0200     b   ppc_exc_fatal_normal
0201     /* SPE floating-point round exception */
0202     PPC_REG_STORE_UPDATE    r1, -EXC_GENERIC_SIZE(r1)
0203     PPC_REG_STORE   r3, GPR3_OFFSET(r1)
0204     li  r3, 34
0205     b   ppc_exc_fatal_normal
0206     /* Performance monitor */
0207     PPC_REG_STORE_UPDATE    r1, -EXC_GENERIC_SIZE(r1)
0208     PPC_REG_STORE   r3, GPR3_OFFSET(r1)
0209     li  r3, 35
0210     b   ppc_exc_fatal_normal