ss555/start/iss555.c

0001 /*
0002  *  Intec SS555 initialization routines.
0003  */
0004
0005 /*
0006  *  SS555 port sponsored by Defence Research and Development Canada - Suffield
0007  *  Copyright (C) 2004, Real-Time Systems Inc. (querbach@realtime.bc.ca)
0008  *
0009  *  Derived from c/src/lib/libbsp/powerpc/mbx8xx/startup/imbx8xx.c:
0010  *
0011  *  Copyright (c) 1999, National Research Council of Canada
0012  *
0013  *  The license and distribution terms for this file may be
0014  *  found in the file LICENSE in this distribution or at
0015  *  http://www.rtems.org/license/LICENSE.
0016  */
0017
0018 #include <bsp.h>
0019
0020 SPR_RW(ICTRL);
0021 SPR_RW(PPC_DEC);
0022 SPR_RW(TBWU);
0023 SPR_RW(TBWL);
0024 SPR_RO(IMMR);
0025 SPR_RW(MI_GRA);
0026 SPR_RW(L2U_GRA);
0027 SPR_RW(BBCMCR);
0028
0029 extern char int_ram_top[];      /* top of internal ram */
0030
0031 /*
0032  *  Initialize SS555
0033  */
0034 void _InitSS555 (void)
0035 {
0036   register uint32_t plprcr, msr;
0037
0038   /*
0039    * Initialize the System Protection Control Register (SYPCR).
0040    * The SYPCR can only be written once after Reset.
0041    */
0042   usiu.sypcr =
0043       USIU_SYPCR_SWTC(WATCHDOG_TIMEOUT) /* set watchdog timeout */
0044     | USIU_SYPCR_BMT(0xFF)      /* set bus monitor timeout */
0045     | USIU_SYPCR_BME            /* enable bus monitor */
0046     | USIU_SYPCR_SWF            /* watchdog halted in freeze */
0047 #if WATCHDOG_TIMEOUT != 0xFFFF
0048     | USIU_SYPCR_SWE            /* enable watchdog */
0049 #endif
0050     | USIU_SYPCR_SWRI           /* watchdog forces reset */
0051     | USIU_SYPCR_SWP;           /* prescale watchdog by 2048 */
0052
0053   TICKLE_WATCHDOG();            /* restart watchdog timer */
0054
0055   /*
0056    * Re-tune the PLL to the desired system clock frequency.
0057    */
0058   usiu.plprck = USIU_UNLOCK_KEY;    /* unlock PLPRCR */
0059   usiu.plprcr =
0060       USIU_PLPRCR_TEXPS         /* assert TEXP always */
0061     | USIU_PLPRCR_MF(BSP_CLOCK_HZ / BSP_CRYSTAL_HZ);
0062                     /* PLL multiplication factor */
0063   usiu.plprck = 0;          /* lock PLPRCR */
0064
0065   while (((plprcr = usiu.plprcr) & USIU_PLPRCR_SPLS) == 0)
0066     ;                   /* wait for PLL to re-lock */
0067
0068   /*
0069    * Enable the timebase and decrementer, then initialize decrementer
0070    * register to a large value to guarantee that a decrementer interrupt
0071    * will not be generated before the kernel is fully initialized.
0072    * Initialize the timebase register to zero.
0073    */
0074   usiu.tbscrk = USIU_UNLOCK_KEY;
0075   usiu.tbscr |= USIU_TBSCR_TBE;     /* enable time base and decrementer */
0076   usiu.tbscrk = 0;
0077
0078   usiu.tbk = USIU_UNLOCK_KEY;
0079   _write_PPC_DEC(0x7FFFFFFF);
0080   _write_TBWU(0x00000000 );
0081   _write_TBWL(0x00000000 );
0082   usiu.tbk = 0;
0083
0084   /*
0085    * Run the Inter-Module Bus at full speed.
0086    */
0087   imb.uimb.umcr &= ~UIMB_UMCR_HSPEED;
0088
0089   /*
0090    * Initialize Memory Controller for External RAM
0091    *
0092    * Initialize the Base and Option Registers (BR0-BR7 and OR0-OR7).  Note
0093    * that for all chip selects, ORx should be programmed before BRx.
0094    *
0095    * If booting from internal flash ROM, configure the external RAM to
0096    * extend the internal RAM.  If booting from external RAM, leave it at
0097    * zero but set it up appropriately.
0098    */
0099   usiu.memc[0]._or =
0100       USIU_MEMC_OR_512K         /* bank size */
0101     | USIU_MEMC_OR_SCY(0)       /* wait states in first beat of burst */
0102     | USIU_MEMC_OR_BSCY(0);     /* wait states in subsequent beats */
0103
0104   usiu.memc[0]._br =
0105       USIU_MEMC_BR_BA(_read_IMMR() & IMMR_FLEN
0106         ? (uint32_t)int_ram_top : 0)    /* base address */
0107     | USIU_MEMC_BR_PS32         /* 32-bit data bus */
0108     | USIU_MEMC_BR_TBDIP        /* toggle bdip */
0109     | USIU_MEMC_BR_V;           /* base register valid */
0110
0111   /*
0112    * Initialize Memory Controller for External CPLD
0113    *
0114    * The SS555 board includes a CPLD to control on-board features and
0115    * off-board devices.  (Configuration taken from Intec's hwhook.c)
0116    */
0117   usiu.memc[3]._or =
0118       USIU_MEMC_OR_16M          /* bank size */
0119     | USIU_MEMC_OR_CSNT         /* negate CS/WE early */
0120     | USIU_MEMC_OR_ACS_HALF     /* assert CS half cycle after address */
0121     | USIU_MEMC_OR_SCY(15)      /* wait states in first beat of burst */
0122     | USIU_MEMC_OR_TRLX;        /* relaxed timing */
0123
0124   usiu.memc[3]._br =
0125       USIU_MEMC_BR_BA(&cpld)        /* base address */
0126     | USIU_MEMC_BR_PS16         /* 16-bit data bus */
0127     | USIU_MEMC_BR_BI           /* inhibit bursting */
0128     | USIU_MEMC_BR_V;           /* base register valid */
0129
0130   /*
0131    * Disable show cycles and serialization so that burst accesses will work
0132    * properly.  A different value, such as 0x0, may be more appropriate for
0133    * debugging, but can be set with the debugger, if needed.
0134    */
0135   _write_ICTRL(0x00000007);
0136
0137   /*
0138    * Set up Burst Buffer Controller (BBC)
0139    */
0140   _write_BBCMCR(
0141       BBCMCR_ETRE           /* enable exception relocation */
0142     | BBCMCR_BE);           /* enable burst accesses */
0143   _isync;
0144
0145   _CPU_MSR_GET(msr);
0146   msr |= MSR_IP;        /* set prefix for exception relocation */
0147   _CPU_MSR_SET(msr);
0148 }