ss555/start/irq_init.c

0001 /*
0002  * irq_init.c
0003  *
0004  *  This file contains the implementation of rtems initialization
0005  *  related to interrupt handling.
0006  */
0007
0008 /*
0009  *  MPC5xx port sponsored by Defence Research and Development Canada - Suffield
0010  *  Copyright (C) 2004, Real-Time Systems Inc. (querbach@realtime.bc.ca)
0011  *
0012  *  Derived from libbsp/powerpc/mbx8xx/irq/irq_init.c:
0013  *
0014  *  CopyRight (C) 2001 valette@crf.canon.fr
0015  *
0016  *  The license and distribution terms for this file may be
0017  *  found in the file LICENSE in this distribution or at
0018  *  http://www.rtems.org/license/LICENSE.
0019  */
0020
0021 #include <rtems.h>
0022 #include <mpc5xx.h>
0023 #include <libcpu/vectors.h>
0024 #include <libcpu/raw_exception.h>
0025 #include <bsp/irq.h>
0026
0027 extern rtems_exception_handler_t dispatch_irq_handler;
0028
0029 volatile unsigned int ppc_cached_irq_mask;
0030
0031 /*
0032  * default methods
0033  */
0034 static void nop_hdl(rtems_irq_hdl_param ignored)
0035 {
0036 }
0037
0038 static void nop_irq_enable(const struct __rtems_irq_connect_data__*ignored)
0039 {
0040 }
0041
0042 static void nop_raw_enable(
0043   const struct __rtems_raw_except_connect_data__*ignored
0044 )
0045 {
0046 }
0047
0048 static int irq_is_connected(const struct __rtems_irq_connect_data__*ignored)
0049 {
0050   return 0;
0051 }
0052
0053 static int raw_is_connected(const struct __rtems_raw_except_connect_data__*ignored)
0054 {
0055   return 0;
0056 }
0057
0058 static rtems_irq_connect_data     rtemsIrq[CPU_IRQ_COUNT];
0059 static rtems_irq_global_settings  initial_config;
0060 static rtems_irq_connect_data     defaultIrq = {
0061   0,                /* vector */
0062   nop_hdl,          /* hdl */
0063   NULL,             /* handle */
0064   nop_irq_enable,   /* on */
0065   nop_irq_enable,   /* off */
0066   irq_is_connected  /* isOn */
0067 };
0068
0069 static rtems_irq_prio irqPrioTable[CPU_IRQ_COUNT]={
0070   /*
0071    * actual priorities for interrupt :
0072    *   0   means that only current interrupt is masked
0073    *   255 means all other interrupts are masked
0074    */
0075   /*
0076    * USIU interrupts.
0077    */
0078   7,7, 6,6, 5,5, 4,4, 3,3, 2,2, 1,1, 0,0,
0079   /*
0080    * UIMB Interrupts
0081    *
0082    * Note that the first 8 UIMB interrupts overlap the 8 external USIU
0083    * interrupts.
0084    */
0085                           0, 0, 0, 0, 0, 0, 0, 0,
0086   0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0087   /*
0088    * Processor exceptions handled as interrupts
0089    */
0090   0
0091 };
0092
0093 static void CPU_USIU_irq_init(void)
0094 {
0095   /*
0096    * In theory we should initialize two registers at least : SIMASK and
0097    * SIEL. SIMASK is reset at 0 value meaning no interrupts.  If someone
0098    * find a reasonnable value for SIEL, and the need to change it, please
0099    * feel free to add it here.
0100    */
0101   ppc_cached_irq_mask = 0;
0102   usiu.simask = ppc_cached_irq_mask;
0103   usiu.sipend = 0xffff0000;
0104   usiu.siel = usiu.siel;
0105 }
0106
0107 /*
0108  * Initialize UIMB interrupt management
0109  */
0110 static void CPU_UIMB_irq_init(void)
0111 {
0112 }
0113
0114 void CPU_rtems_irq_mng_init(unsigned cpuId)
0115 {
0116   rtems_raw_except_connect_data vectorDesc;
0117   int i;
0118
0119   CPU_USIU_irq_init();
0120   CPU_UIMB_irq_init();
0121   /*
0122    * Initialize RTEMS management interrupt table
0123    */
0124     /*
0125      * re-init the rtemsIrq table
0126      */
0127     for (i = 0; i < CPU_IRQ_COUNT; i++) {
0128       rtemsIrq[i]      = defaultIrq;
0129       rtemsIrq[i].name = i;
0130     }
0131     /*
0132      * Init initial Interrupt management config
0133      */
0134     initial_config.irqNb        = CPU_IRQ_COUNT;
0135     initial_config.defaultEntry = defaultIrq;
0136     initial_config.irqHdlTbl    = rtemsIrq;
0137     initial_config.irqBase      = CPU_ASM_IRQ_VECTOR_BASE;
0138     initial_config.irqPrioTbl   = irqPrioTable;
0139
0140     if (!CPU_rtems_irq_mngt_set(&initial_config)) {
0141       /*
0142        * put something here that will show the failure...
0143        */
0144       rtems_panic("Unable to initialize RTEMS interrupt Management\n");
0145     }
0146
0147   /*
0148    * We must connect the raw irq handler for the two
0149    * expected interrupt sources : decrementer and external interrupts.
0150    */
0151     vectorDesc.exceptIndex = ASM_DEC_VECTOR;
0152     vectorDesc.hdl.vector  = ASM_DEC_VECTOR;
0153     vectorDesc.hdl.raw_hdl = dispatch_irq_handler;
0154     vectorDesc.on          = nop_raw_enable;
0155     vectorDesc.off         = nop_raw_enable;
0156     vectorDesc.isOn        = raw_is_connected;
0157     if (!mpc5xx_set_exception (&vectorDesc)) {
0158       rtems_panic("Unable to initialize RTEMS decrementer raw exception\n");
0159     }
0160     vectorDesc.exceptIndex = ASM_EXT_VECTOR;
0161     vectorDesc.hdl.vector  = ASM_EXT_VECTOR;
0162     if (!mpc5xx_set_exception (&vectorDesc)) {
0163       rtems_panic("Unable to initialize RTEMS external raw exception\n");
0164     }
0165 }