ss555/include/bsp.h

0001 /**
0002  * @file
0003  *
0004  * @ingroup RTEMSBSPsPowerPCSS555
0005  *
0006  * @brief Global BSP definitions.
0007  */
0008
0009 /*
0010  *  This file includes definitions for the Intec SS555.
0011  */
0012
0013 /*
0014  *  SS555 port sponsored by Defence Research and Development Canada - Suffield
0015  *  Copyright (C) 2004, Real-Time Systems Inc. (querbach@realtime.bc.ca)
0016  *
0017  *  Derived from c/src/lib/libbsp/powerpc/mbx8xx/include/bsp.h:
0018  *
0019  *  COPYRIGHT (c) 1989-1998.
0020  *  On-Line Applications Research Corporation (OAR).
0021  *
0022  *  The license and distribution terms for this file may be
0023  *  found in the file LICENSE in this distribution or at
0024  *  http://www.rtems.org/license/LICENSE.
0025  */
0026
0027 #ifndef LIBBSP_POWERPC_SS555_BSP_H
0028 #define LIBBSP_POWERPC_SS555_BSP_H
0029
0030 /**
0031  * @defgroup RTEMSBSPsPowerPCSS555 SS555
0032  *
0033  * @ingroup RTEMSBSPsPowerPC
0034  *
0035  * @brief SS555 Board Support Package.
0036  *
0037  * @{
0038  */
0039
0040 #include <bspopts.h>
0041
0042 #ifdef ASM
0043
0044 #define eie     0x050   /* External Interrupt Enable Register */
0045 #define eid     0x051   /* External Interrupt Disable Register */
0046 #define nri     0x052   /* Non-Recoverable Interrupt Register */
0047
0048 #else /* !ASM */
0049
0050 #include <bsp/default-initial-extension.h>
0051
0052 #include <rtems.h>
0053 #include <mpc5xx.h>
0054 #include <mpc5xx/console.h>
0055 #include <libcpu/vectors.h>
0056 #include <bsp/irq.h>
0057
0058 #ifdef __cplusplus
0059 extern "C" {
0060 #endif
0061
0062 /*
0063  * Clock definitions
0064  */
0065
0066 #define BSP_CRYSTAL_HZ   4000000    /* crystal frequency, Hz */
0067 #define BSP_CLOCK_HZ    40000000    /* CPU clock frequency, Hz */
0068
0069 /*
0070  * I/O definitions
0071  *
0072  * The SS555 board includes a CPLD to control on-board features and
0073  * off-board devices.
0074  */
0075 typedef struct cpld_ {
0076   uint8_t   cs3a[32];       /* Chip select 3A */
0077   uint8_t   pad0[0x200000 - 0x000020];
0078
0079   uint8_t   cs3b[32];       /* Chip select 3B */
0080   uint8_t   pad2[0x400000 - 0x200020];
0081
0082   uint8_t   cs3c[32];       /* Chip select 3C */
0083   uint8_t   pad4[0x600000 - 0x400020];
0084
0085   uint8_t   cs3d[32];       /* Chip select 3D */
0086   uint8_t   pad6[0x800000 - 0x600020];
0087
0088   uint8_t   serial_ints;    /* Enable/disable serial interrupts */
0089   uint8_t   serial_resets;  /* Enable/disable serial resets */
0090   uint8_t   serial_ack; /* Acknowledge serial transfers */
0091   uint8_t   pad8[0xA00000 - 0x800003];
0092
0093   uint8_t   iflash_writess; /* Enable/disable internal-flash writes */
0094   uint8_t   nflash_writess; /* Enable/disable NAND-flash writes */
0095   uint8_t   padA[0xC00000 - 0xA00002];
0096 } cpld_t;
0097
0098 extern volatile cpld_t cpld;              /* defined in linkcmds */
0099
0100 /* clock/p_clock.c */
0101 extern int BSP_disconnect_clock_handler (void);
0102
0103 extern int BSP_connect_clock_handler (rtems_irq_hdl hdl);
0104
0105 /*
0106  *  Prototypes for methods called from .S to support dependency tracking.
0107  */
0108 void _InitSS555(void);
0109
0110 #ifdef __cplusplus
0111 }
0112 #endif
0113
0114 #endif /* !ASM */
0115
0116 /** @} */
0117
0118 #endif