shared/start/start.S

0001 /*
0002  *  start.S :     RTEMS entry point
0003  *
0004  *  Copyright (C) 1999 Eric Valette. valette@crf.canon.fr
0005  *
0006  *  The license and distribution terms for this file may be
0007  *  found in the file LICENSE in this distribution or at
0008  *  http://www.rtems.org/license/LICENSE.
0009  *
0010  */
0011
0012 #include <rtems/asm.h>
0013 #include <libcpu/powerpc-utility.h>
0014
0015 #include <libcpu/io.h>
0016 #include <libcpu/bat.h>
0017 #include <bspopts.h>
0018
0019 #define SYNC \
0020     sync; \
0021     isync
0022
0023 #define KERNELBASE  0x0
0024
0025 #define MONITOR_ENTER           \
0026     mfmsr   r10     ;   \
0027     ori r10,r10,MSR_IP  ;   \
0028     mtmsr   r10     ;   \
0029     li  r10,0x63    ;   \
0030     sc
0031
0032     .text
0033     .globl  __rtems_entry_point
0034     .type   __rtems_entry_point,@function
0035 __rtems_entry_point:
0036 #ifdef DEBUG_EARLY_START
0037     MONITOR_ENTER
0038 #endif
0039
0040 /*
0041  * PREP
0042  * This is jumped to on prep systems right after the kernel is relocated
0043  * to its proper place in memory by the boot loader.  The expected layout
0044  * of the regs is:
0045  *   r3: ptr to residual data
0046  *   r4: initrd_start or if no initrd then 0
0047  *   r5: initrd_end - unused if r4 is 0
0048  *   r6: Start of command line string
0049  *   r7: End of command line string
0050  *
0051  *   The Prep boot loader insure that the MMU is currently off...
0052  *
0053  */
0054
0055     mr  r31,r3          /* save parameters */
0056     mr  r30,r4
0057     mr  r29,r5
0058     mr  r28,r6
0059     mr  r27,r7
0060
0061 #ifdef __ALTIVEC__
0062     /* enable altivec; gcc may use it! */
0063     mfmsr r0
0064     oris  r0, r0, (1<<(31-16-6))
0065     mtmsr r0
0066     isync
0067     /*
0068      * set vscr and vrsave to known values
0069      */
0070     li    r0, 0
0071     mtvrsave r0
0072     vxor   0,0,0
0073     mtvscr 0
0074 #endif
0075
0076     /*
0077      * Make sure we have nothing in BATS and TLB
0078      */
0079     bl  CPU_clear_bats_early
0080     bl  flush_tlbs
0081 /*
0082  * Use the first pair of BAT registers to map the 1st 256MB
0083  * of RAM to KERNELBASE.
0084  */
0085     lis r11,KERNELBASE@h
0086 /* set up BAT registers for 604 */
0087     ori r11,r11,0x1ffe
0088     li  r8,2            /* R/W access */
0089     isync
0090     mtspr   DBAT0L,r8       /* N.B. 6xx (not 601) have valid */
0091     mtspr   DBAT0U,r11      /* bit in upper BAT register */
0092     mtspr   IBAT0L,r8
0093     mtspr   IBAT0U,r11
0094     isync
0095 /*   Map section where residual is located if outside
0096  *   the first 256Mb of RAM.  This is to support cases
0097  *   where the available system memory is larger than
0098  *   256Mb of RAM.
0099  */
0100     mr  r9, r1 /* Get where residual was mapped */
0101     lis r12,0xf0000000@h
0102     and r9,r9,r12
0103     cmpi    0,1,r9, 0
0104     beq enter_C_code
0105     isync
0106     ori r11,r9,0x1ffe
0107     mtspr   DBAT1L,r8       /* N.B. 6xx (not 601) have valid */
0108     mtspr   DBAT1U,r11      /* bit in upper BAT register */
0109     mtspr   IBAT1L,r8
0110     mtspr   IBAT1U,r11
0111     isync
0112
0113 /*
0114  * we now have the 1st 256M of ram mapped with the bats. We are still
0115  * running on the bootloader stack and cannot switch to an RTEMS allocated
0116  * init stack before copying the residual data that may have been set just after
0117  * rtems_end address. This bug has been experienced on MVME2304. Thank to
0118  * Till Straumann <strauman@SLAC.Stanford.EDU> for hunting it and suggesting
0119  * the appropriate code.
0120  */
0121
0122 enter_C_code:
0123     /*
0124      * Initialize start stack.  The stacks are statically allocated and
0125      * properly aligned.
0126      */
0127     LA  r1, _ISR_Stack_area_end
0128     subi    r1, r1, PPC_DEFAULT_CACHE_LINE_SIZE
0129     li  r0, 0
0130     stw r0, 0(r1)
0131
0132     bl  MMUon
0133     bl      __eabi  /* setup EABI and SYSV environment */
0134     bl  zero_bss
0135     /*
0136      * restore prep boot params
0137      */
0138     mr  r3,r31
0139     mr  r4,r30
0140     mr  r5,r29
0141     mr  r6,r28
0142     mr  r7,r27
0143     bl  save_boot_params
0144
0145     /*
0146      * We are now in a environment that is totally independent from
0147      * bootloader setup.
0148      */
0149     /* pass result of 'save_boot_params' to 'boot_card' in R3 */
0150     bl  boot_card
0151     bl  _return_to_ppcbug
0152
0153     .globl  MMUon
0154     .type   MMUon,@function
0155 MMUon:
0156     mfmsr   r0
0157     ori r0,r0, MSR_IP | MSR_RI | MSR_IR | MSR_DR | MSR_EE | MSR_FE0 | MSR_FE1 | MSR_FP
0158 #if (PPC_HAS_FPU == 0)
0159     xori    r0, r0, MSR_EE | MSR_IP | MSR_FP
0160 #else
0161     xori    r0, r0, MSR_EE | MSR_IP | MSR_FE0 | MSR_FE1
0162 #endif
0163     mflr    r11
0164     mtsrr0  r11
0165     mtsrr1  r0
0166     SYNC
0167     rfi
0168
0169     .globl  MMUoff
0170     .type   MMUoff,@function
0171 MMUoff:
0172     mfmsr   r0
0173     ori r0,r0,MSR_IR| MSR_DR | MSR_IP
0174     mflr    r11
0175     xori    r0,r0,MSR_IR|MSR_DR
0176     mtsrr0  r11
0177     mtsrr1  r0
0178     SYNC
0179     rfi
0180
0181     .globl  _return_to_ppcbug
0182     .type   _return_to_ppcbug,@function
0183
0184 _return_to_ppcbug:
0185     mflr    r30
0186     bl  MMUoff
0187     MONITOR_ENTER
0188     bl  MMUon
0189     mtctr   r30
0190     bctr
0191
0192 flush_tlbs:
0193     lis r20, 0x1000
0194 1:  addic.  r20, r20, -0x1000
0195     tlbie   r20, 0
0196     bgt 1b
0197     sync
0198     blr