shared/start/bsp-start-zero.S

0001 /* SPDX-License-Identifier: BSD-2-Clause */
0002
0003 /**
0004  * @file
0005  *
0006  * @ingroup bsp_start
0007  *
0008  * @brief bsp_start_zero() implementation.
0009  */
0010
0011 /*
0012  * Copyright (C) 2010, 2014 embedded brains GmbH & Co. KG
0013  *
0014  * Redistribution and use in source and binary forms, with or without
0015  * modification, are permitted provided that the following conditions
0016  * are met:
0017  * 1. Redistributions of source code must retain the above copyright
0018  *    notice, this list of conditions and the following disclaimer.
0019  * 2. Redistributions in binary form must reproduce the above copyright
0020  *    notice, this list of conditions and the following disclaimer in the
0021  *    documentation and/or other materials provided with the distribution.
0022  *
0023  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
0024  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
0025  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
0026  * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
0027  * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
0028  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
0029  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
0030  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
0031  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
0032  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
0033  * POSSIBILITY OF SUCH DAMAGE.
0034  */
0035
0036 #include <rtems/asm.h>
0037 #include <libcpu/powerpc-utility.h>
0038 #include <bspopts.h>
0039
0040     .globl bsp_start_zero
0041     .globl bsp_start_zero_begin
0042     .globl bsp_start_zero_end
0043     .globl bsp_start_zero_size
0044
0045     .section ".bsp_start_text", "ax"
0046     .type bsp_start_zero, @function
0047 bsp_start_zero:
0048 bsp_start_zero_begin:
0049     li  r0, 0
0050     subi    r11, r3, 1
0051     CLEAR_RIGHT_IMMEDIATE   r11, r11, PPC_CACHE_ALIGN_POWER
0052     addi    r10, r11, PPC_CACHE_ALIGNMENT
0053     subf    r11, r3, r10
0054     COMPARE_LOGICAL cr7, r11, r4
0055     add r9, r3, r4
0056     ble-    cr7, head_end_done
0057     mr  r10, r9
0058 head_end_done:
0059     subf    r11, r3, r10
0060     addi    r11, r11, 1
0061     mtctr   r11
0062
0063     /* Head loop */
0064     b   head_loop_update
0065 head_loop_begin:
0066     stb r0, 0(r3)
0067     addi    r3, r3, 1
0068 head_loop_update:
0069     bdnz+   head_loop_begin
0070
0071     subf    r11, r3, r9
0072     SHIFT_RIGHT_IMMEDIATE   r11, r11, PPC_CACHE_ALIGN_POWER
0073     addi    r11, r11, 1
0074     mtctr   r11
0075
0076     /* Main loop */
0077     b   main_loop_update
0078 main_loop_begin:
0079 #if BSP_DATA_CACHE_ENABLED
0080     dcbz    r0, r3
0081     dcbf    r0, r3
0082 #else
0083   #if PPC_CACHE_ALIGNMENT == 32 || PPC_CACHE_ALIGNMENT == 64
0084     stw r0, 0(r3)
0085     stw r0, 4(r3)
0086     stw r0, 8(r3)
0087     stw r0, 12(r3)
0088     stw r0, 16(r3)
0089     stw r0, 20(r3)
0090     stw r0, 24(r3)
0091     stw r0, 28(r3)
0092     #if PPC_CACHE_ALIGNMENT == 64
0093     stw r0, 32(r3)
0094     stw r0, 36(r3)
0095     stw r0, 40(r3)
0096     stw r0, 44(r3)
0097     stw r0, 48(r3)
0098     stw r0, 52(r3)
0099     stw r0, 56(r3)
0100     stw r0, 60(r3)
0101     #endif
0102   #else
0103     #error "unsupported cache alignment"
0104   #endif
0105 #endif
0106     addi    r3, r3, PPC_CACHE_ALIGNMENT
0107 main_loop_update:
0108     bdnz+   main_loop_begin
0109
0110     subf    r9, r3, r9
0111     addi    r9, r9, 1
0112     mtctr   r9
0113
0114     /* Tail loop */
0115     b   tail_loop_update
0116 tail_loop_begin:
0117     stb r0, 0(r3)
0118     addi    r3, r3, 1
0119 tail_loop_update:
0120     bdnz+   tail_loop_begin
0121
0122     /* Return */
0123     sync
0124     isync
0125     blr
0126
0127 bsp_start_zero_end:
0128     .set bsp_start_zero_size, bsp_start_zero_end - bsp_start_zero_begin