shared/pci/detect_raven_bridge.c

0001 #include <libcpu/io.h>
0002 #include <libcpu/spr.h>
0003 #include <inttypes.h>
0004
0005 #include <bsp.h>
0006 #include <bsp/pci.h>
0007 #include <bsp/consoleIo.h>
0008 #include <bsp/residual.h>
0009 #include <bsp/openpic.h>
0010 #include <bsp/irq.h>
0011
0012 #include <rtems/bspIo.h>
0013 #include <libcpu/cpuIdent.h>
0014
0015 #define SHOW_RAVEN_SETTINGS
0016
0017 #define RAVEN_MPIC_IOSPACE_ENABLE  0x0001
0018 #define RAVEN_MPIC_MEMSPACE_ENABLE 0x0002
0019 #define RAVEN_MASTER_ENABLE        0x0004
0020 #define RAVEN_PARITY_CHECK_ENABLE  0x0040
0021 #define RAVEN_SYSTEM_ERROR_ENABLE  0x0100
0022 #define RAVEN_CLEAR_EVENTS_MASK    0xf9000000
0023
0024 #define RAVEN_MPIC_MEREN    ((volatile unsigned *)0xfeff0020)
0025 #define RAVEN_MPIC_MERST    ((volatile unsigned *)0xfeff0024)
0026 #define MEREN_VAL           0x2f00
0027
0028 #define pci BSP_pci_configuration
0029
0030 extern const pci_config_access_functions pci_direct_functions;
0031 extern const pci_config_access_functions pci_indirect_functions;
0032
0033 #if defined(mot_ppc_mvme2100)
0034 /* FIXME - this should really be in a separate file - the 2100 doesn't
0035  *         have a raven chip so there is no point having 2100 code here
0036  */
0037
0038 extern unsigned int EUMBBAR;
0039
0040 void detect_host_bridge(void)
0041 {
0042   /*
0043    * If the processor is an 8240 or an 8245 then the PIC is built
0044    * in instead of being on the PCI bus. The MVME2100 is using Processor
0045    * Address Map B (CHRP) although the Programmer's Reference Guide says
0046    * it defaults to Map A.
0047    */
0048   /* We have an EPIC Interrupt Controller  */
0049   OpenPIC = (volatile struct OpenPIC *) (EUMBBAR + BSP_OPEN_PIC_BASE_OFFSET);
0050   pci.pci_functions = &pci_indirect_functions;
0051   pci.pci_config_addr = (volatile unsigned char *) 0xfec00000;
0052   pci.pci_config_data = (volatile unsigned char *) 0xfee00000;
0053 }
0054
0055 #else
0056
0057 #if 0
0058 /* Unfortunately, PCI config space access to empty slots generates
0059  * a 'signalled master abort' condition --> we can't really use
0060  * the machine check interrupt for memory probing unless
0061  * we use probing for PCI scanning also (which would make
0062  * all that code either BSP dependent or requiring yet another
0063  * API, sigh...).
0064  * So for the moment, we just don't use MCP on all mvme2xxx
0065  * boards (using the generic, hostbridge-independent 'clear'
0066  * implementation [generic_clear_hberrs.c]).
0067  */
0068 /*
0069  * enableMCP: whether to enable MCP checkstop / machine check interrupts
0070  *            on the hostbridge and in HID0.
0071  *
0072  *            NOTE: HID0 and MEREN are left alone if this flag is 0
0073  *
0074  * quiet    : be silent
0075  *
0076  * RETURNS  : raven MERST register contents (lowermost 16 bits), 0 if
0077  *            there were no errors
0078  */
0079 unsigned long
0080 _BSP_clear_hostbridge_errors(int enableMCP, int quiet)
0081 {
0082 unsigned merst;
0083
0084     merst = in_be32(RAVEN_MPIC_MERST);
0085     /* write back value to clear status */
0086     out_be32(RAVEN_MPIC_MERST, merst);
0087
0088     if (enableMCP) {
0089       if (!quiet)
0090         printk("Enabling MCP generation on hostbridge errors\n");
0091       out_be32(RAVEN_MPIC_MEREN, MEREN_VAL);
0092     } else {
0093       out_be32(RAVEN_MPIC_MEREN, 0);
0094       if ( !quiet && enableMCP ) {
0095         printk("leaving MCP interrupt disabled\n");
0096       }
0097     }
0098     return (merst & 0xffff);
0099 }
0100 #endif
0101
0102 void detect_host_bridge(void)
0103 {
0104   PPC_DEVICE *hostbridge;
0105   uint32_t id0;
0106   uint32_t tmp;
0107
0108   /*
0109    * This code assumes that the host bridge is located at
0110    * bus 0, dev 0, func 0 AND that the old pre PCI 2.1
0111    * standard devices detection mechanism that was used on PC
0112    * (still used in BSD source code) works.
0113    */
0114   hostbridge=residual_find_device(&residualCopy, PROCESSORDEVICE, NULL,
0115                   BridgeController,
0116                   PCIBridge, -1, 0);
0117   if (hostbridge) {
0118     if (hostbridge->DeviceId.Interface==PCIBridgeIndirect) {
0119       pci.pci_functions=&pci_indirect_functions;
0120       /* Should be extracted from residual data,
0121        * indeed MPC106 in CHRP mode is different,
0122        * but we should not use residual data in
0123        * this case anyway.
0124        */
0125       pci.pci_config_addr = ((volatile unsigned char *)
0126                   (ptr_mem_map->io_base+0xcf8));
0127       pci.pci_config_data = ptr_mem_map->io_base+0xcfc;
0128     } else if(hostbridge->DeviceId.Interface==PCIBridgeDirect) {
0129       pci.pci_functions=&pci_direct_functions;
0130       pci.pci_config_data=(unsigned char *) 0x80800000;
0131     } else {
0132     }
0133   } else {
0134     /* Let us try by experimentation at our own risk! */
0135     pci.pci_functions = &pci_direct_functions;
0136     /* On all direct bridges I know the host bridge itself
0137      * appears as device 0 function 0.
0138          */
0139     pci_read_config_dword(0, 0, 0, PCI_VENDOR_ID, &id0);
0140     if (id0==~0U) {
0141       pci.pci_functions = &pci_indirect_functions;
0142       pci.pci_config_addr = ((volatile unsigned char*)
0143                   (ptr_mem_map->io_base+0xcf8));
0144       pci.pci_config_data = ((volatile unsigned char*)ptr_mem_map->io_base+0xcfc);
0145     }
0146     /* Here we should check that the host bridge is actually
0147      * present, but if it not, we are in such a desperate
0148      * situation, that we probably can't even tell it.
0149      */
0150   }
0151   pci_read_config_dword(0, 0, 0, 0, &id0);
0152 #ifdef SHOW_RAVEN_SETTINGS
0153   printk("idreg 0 = 0x%" PRIu32 "\n",id0);
0154 #endif
0155   if((id0 == PCI_VENDOR_ID_MOTOROLA +
0156       (PCI_DEVICE_ID_MOTOROLA_RAVEN<<16)) ||
0157      (id0 == PCI_VENDOR_ID_MOTOROLA +
0158       (PCI_DEVICE_ID_MOTOROLA_HAWK<<16))) {
0159     /*
0160      * We have a Raven bridge. We will get information about its settings
0161      */
0162     pci_read_config_dword(0, 0, 0, PCI_COMMAND, &id0);
0163 #ifdef SHOW_RAVEN_SETTING
0164     printk("RAVEN PCI command register = %x\n",id0);
0165 #endif
0166     id0 |= RAVEN_CLEAR_EVENTS_MASK;
0167     pci_write_config_dword(0, 0, 0, PCI_COMMAND, id0);
0168     pci_read_config_dword(0, 0, 0, PCI_COMMAND, &id0);
0169 #ifdef SHOW_RAVEN_SETTING
0170     printk("After error clearing RAVEN PCI command register = %x\n",id0);
0171 #endif
0172
0173     if (id0 & RAVEN_MPIC_IOSPACE_ENABLE) {
0174       pci_read_config_dword(0, 0, 0,PCI_BASE_ADDRESS_0, &tmp);
0175 #ifdef SHOW_RAVEN_SETTING
0176       printk("Raven MPIC is accessed via IO Space Access at address : %x\n",(tmp & ~0x1));
0177 #endif
0178     }
0179     if (id0 & RAVEN_MPIC_MEMSPACE_ENABLE) {
0180       pci_read_config_dword(0, 0, 0,PCI_BASE_ADDRESS_1, &tmp);
0181 #ifdef SHOW_RAVEN_SETTING
0182       printk("Raven MPIC is accessed via memory Space Access at address : %x\n", tmp);
0183 #endif
0184       OpenPIC=(volatile struct OpenPIC *) (tmp + PREP_ISA_MEM_BASE);
0185       printk("OpenPIC found at %p.\n", OpenPIC);
0186     }
0187   }
0188
0189 #if BSP_PCI_IRQ_NUMBER > 0
0190   if (OpenPIC == (volatile struct OpenPIC *)0) {
0191     rtems_panic("OpenPic Not found\n");
0192   }
0193 #endif
0194
0195 }
0196
0197 #endif