shared/exceptions/ppc_exc_fatal.S

0001 /* SPDX-License-Identifier: BSD-2-Clause */
0002
0003 /*
0004  * Copyright (C) 2011, 2017 embedded brains GmbH & Co. KG
0005  *
0006  * Redistribution and use in source and binary forms, with or without
0007  * modification, are permitted provided that the following conditions
0008  * are met:
0009  * 1. Redistributions of source code must retain the above copyright
0010  *    notice, this list of conditions and the following disclaimer.
0011  * 2. Redistributions in binary form must reproduce the above copyright
0012  *    notice, this list of conditions and the following disclaimer in the
0013  *    documentation and/or other materials provided with the distribution.
0014  *
0015  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
0016  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
0017  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
0018  * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
0019  * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
0020  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
0021  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
0022  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
0023  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
0024  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
0025  * POSSIBILITY OF SUCH DAMAGE.
0026  */
0027
0028 #include <bspopts.h>
0029 #include <rtems/score/percpu.h>
0030 #include <bsp/vectors.h>
0031
0032 #define SCRATCH_REGISTER_0 r3
0033 #define SCRATCH_REGISTER_1 r4
0034
0035     .global ppc_exc_fatal_normal
0036     .global ppc_exc_fatal_critical
0037     .global ppc_exc_fatal_machine_check
0038     .global ppc_exc_fatal_debug
0039
0040 ppc_exc_fatal_critical:
0041
0042     PPC_REG_STORE   SCRATCH_REGISTER_1, GPR4_OFFSET(r1)
0043     mfcsrr0 SCRATCH_REGISTER_1
0044     PPC_REG_STORE   SCRATCH_REGISTER_1, SRR0_FRAME_OFFSET(r1)
0045     mfcsrr1 SCRATCH_REGISTER_1
0046     PPC_REG_STORE   SCRATCH_REGISTER_1, SRR1_FRAME_OFFSET(r1)
0047     b   .Lppc_exc_fatal
0048
0049 ppc_exc_fatal_machine_check:
0050
0051     PPC_REG_STORE   SCRATCH_REGISTER_1, GPR4_OFFSET(r1)
0052     mfmcsrr0    SCRATCH_REGISTER_1
0053     PPC_REG_STORE   SCRATCH_REGISTER_1, SRR0_FRAME_OFFSET(r1)
0054     mfmcsrr1    SCRATCH_REGISTER_1
0055     PPC_REG_STORE   SCRATCH_REGISTER_1, SRR1_FRAME_OFFSET(r1)
0056     b   .Lppc_exc_fatal
0057
0058 ppc_exc_fatal_debug:
0059
0060     PPC_REG_STORE   SCRATCH_REGISTER_1, GPR4_OFFSET(r1)
0061     mfspr   SCRATCH_REGISTER_1, BOOKE_DSRR0
0062     PPC_REG_STORE   SCRATCH_REGISTER_1, SRR0_FRAME_OFFSET(r1)
0063     mfspr   SCRATCH_REGISTER_1, BOOKE_DSRR1
0064     PPC_REG_STORE   SCRATCH_REGISTER_1, SRR1_FRAME_OFFSET(r1)
0065     b   .Lppc_exc_fatal
0066
0067 ppc_exc_fatal_normal:
0068
0069     PPC_REG_STORE   SCRATCH_REGISTER_1, GPR4_OFFSET(r1)
0070     mfsrr0  SCRATCH_REGISTER_1
0071     PPC_REG_STORE   SCRATCH_REGISTER_1, SRR0_FRAME_OFFSET(r1)
0072     mfsrr1  SCRATCH_REGISTER_1
0073     PPC_REG_STORE   SCRATCH_REGISTER_1, SRR1_FRAME_OFFSET(r1)
0074
0075 .Lppc_exc_fatal:
0076
0077     stw r3, EXCEPTION_NUMBER_OFFSET(r1)
0078     mfcr    SCRATCH_REGISTER_1
0079     stw SCRATCH_REGISTER_1, EXC_CR_OFFSET(r1)
0080     mfxer   SCRATCH_REGISTER_1
0081     stw SCRATCH_REGISTER_1, EXC_XER_OFFSET(r1)
0082     mfctr   SCRATCH_REGISTER_1
0083     PPC_REG_STORE   SCRATCH_REGISTER_1, EXC_CTR_OFFSET(r1)
0084     mflr    SCRATCH_REGISTER_1
0085     PPC_REG_STORE   SCRATCH_REGISTER_1, EXC_LR_OFFSET(r1)
0086     PPC_REG_STORE   r0, GPR0_OFFSET(r1)
0087     PPC_REG_STORE   r1, GPR1_OFFSET(r1)
0088     PPC_REG_STORE   r2, GPR2_OFFSET(r1)
0089     PPC_REG_STORE   r5, GPR5_OFFSET(r1)
0090     PPC_REG_STORE   r6, GPR6_OFFSET(r1)
0091     PPC_REG_STORE   r7, GPR7_OFFSET(r1)
0092     PPC_REG_STORE   r8, GPR8_OFFSET(r1)
0093     PPC_REG_STORE   r9, GPR9_OFFSET(r1)
0094     PPC_REG_STORE   r10, GPR10_OFFSET(r1)
0095     PPC_REG_STORE   r11, GPR11_OFFSET(r1)
0096     PPC_REG_STORE   r12, GPR12_OFFSET(r1)
0097     PPC_REG_STORE   r13, GPR13_OFFSET(r1)
0098     PPC_REG_STORE   r14, GPR14_OFFSET(r1)
0099     PPC_REG_STORE   r15, GPR15_OFFSET(r1)
0100     PPC_REG_STORE   r16, GPR16_OFFSET(r1)
0101     PPC_REG_STORE   r17, GPR17_OFFSET(r1)
0102     PPC_REG_STORE   r18, GPR18_OFFSET(r1)
0103     PPC_REG_STORE   r19, GPR19_OFFSET(r1)
0104     PPC_REG_STORE   r20, GPR20_OFFSET(r1)
0105     PPC_REG_STORE   r21, GPR21_OFFSET(r1)
0106     PPC_REG_STORE   r22, GPR22_OFFSET(r1)
0107     PPC_REG_STORE   r23, GPR23_OFFSET(r1)
0108     PPC_REG_STORE   r24, GPR24_OFFSET(r1)
0109     PPC_REG_STORE   r25, GPR25_OFFSET(r1)
0110     PPC_REG_STORE   r26, GPR26_OFFSET(r1)
0111     PPC_REG_STORE   r27, GPR27_OFFSET(r1)
0112     PPC_REG_STORE   r28, GPR28_OFFSET(r1)
0113     PPC_REG_STORE   r29, GPR29_OFFSET(r1)
0114     PPC_REG_STORE   r30, GPR30_OFFSET(r1)
0115     PPC_REG_STORE   r31, GPR31_OFFSET(r1)
0116
0117     /* Enable FPU and/or AltiVec */
0118 #if defined(PPC_MULTILIB_FPU) || defined(PPC_MULTILIB_ALTIVEC)
0119     mfmsr   SCRATCH_REGISTER_1
0120 #ifdef PPC_MULTILIB_FPU
0121     ori SCRATCH_REGISTER_1, SCRATCH_REGISTER_1, MSR_FP
0122 #endif
0123 #ifdef PPC_MULTILIB_ALTIVEC
0124     oris    SCRATCH_REGISTER_1, SCRATCH_REGISTER_1, MSR_VE >> 16
0125 #endif
0126     mtmsr   SCRATCH_REGISTER_1
0127     isync
0128 #endif
0129
0130 #ifdef PPC_MULTILIB_ALTIVEC
0131     li  SCRATCH_REGISTER_1, PPC_EXC_VR_OFFSET(0)
0132     stvx    v0, r1, SCRATCH_REGISTER_1
0133     mfvscr  v0
0134     li  SCRATCH_REGISTER_1, PPC_EXC_VSCR_OFFSET
0135     stvewx  v0, r1, SCRATCH_REGISTER_1
0136     li  SCRATCH_REGISTER_1, PPC_EXC_VR_OFFSET(1)
0137     stvx    v1, r1, SCRATCH_REGISTER_1
0138     li  SCRATCH_REGISTER_1, PPC_EXC_VR_OFFSET(2)
0139     stvx    v2, r1, SCRATCH_REGISTER_1
0140     li  SCRATCH_REGISTER_1, PPC_EXC_VR_OFFSET(3)
0141     stvx    v3, r1, SCRATCH_REGISTER_1
0142     li  SCRATCH_REGISTER_1, PPC_EXC_VR_OFFSET(4)
0143     stvx    v4, r1, SCRATCH_REGISTER_1
0144     li  SCRATCH_REGISTER_1, PPC_EXC_VR_OFFSET(5)
0145     stvx    v5, r1, SCRATCH_REGISTER_1
0146     li  SCRATCH_REGISTER_1, PPC_EXC_VR_OFFSET(6)
0147     stvx    v6, r1, SCRATCH_REGISTER_1
0148     li  SCRATCH_REGISTER_1, PPC_EXC_VR_OFFSET(7)
0149     stvx    v7, r1, SCRATCH_REGISTER_1
0150     li  SCRATCH_REGISTER_1, PPC_EXC_VR_OFFSET(8)
0151     stvx    v8, r1, SCRATCH_REGISTER_1
0152     li  SCRATCH_REGISTER_1, PPC_EXC_VR_OFFSET(9)
0153     stvx    v9, r1, SCRATCH_REGISTER_1
0154     li  SCRATCH_REGISTER_1, PPC_EXC_VR_OFFSET(10)
0155     stvx    v10, r1, SCRATCH_REGISTER_1
0156     li  SCRATCH_REGISTER_1, PPC_EXC_VR_OFFSET(11)
0157     stvx    v11, r1, SCRATCH_REGISTER_1
0158     li  SCRATCH_REGISTER_1, PPC_EXC_VR_OFFSET(12)
0159     stvx    v12, r1, SCRATCH_REGISTER_1
0160     li  SCRATCH_REGISTER_1, PPC_EXC_VR_OFFSET(13)
0161     stvx    v13, r1, SCRATCH_REGISTER_1
0162     li  SCRATCH_REGISTER_1, PPC_EXC_VR_OFFSET(14)
0163     stvx    v14, r1, SCRATCH_REGISTER_1
0164     li  SCRATCH_REGISTER_1, PPC_EXC_VR_OFFSET(15)
0165     stvx    v15, r1, SCRATCH_REGISTER_1
0166     li  SCRATCH_REGISTER_1, PPC_EXC_VR_OFFSET(16)
0167     stvx    v16, r1, SCRATCH_REGISTER_1
0168     li  SCRATCH_REGISTER_1, PPC_EXC_VR_OFFSET(17)
0169     stvx    v17, r1, SCRATCH_REGISTER_1
0170     li  SCRATCH_REGISTER_1, PPC_EXC_VR_OFFSET(18)
0171     stvx    v18, r1, SCRATCH_REGISTER_1
0172     li  SCRATCH_REGISTER_1, PPC_EXC_VR_OFFSET(19)
0173     stvx    v19, r1, SCRATCH_REGISTER_1
0174     li  SCRATCH_REGISTER_1, PPC_EXC_VR_OFFSET(20)
0175     stvx    v20, r1, SCRATCH_REGISTER_1
0176     li  SCRATCH_REGISTER_1, PPC_EXC_VR_OFFSET(21)
0177     stvx    v21, r1, SCRATCH_REGISTER_1
0178     li  SCRATCH_REGISTER_1, PPC_EXC_VR_OFFSET(22)
0179     stvx    v22, r1, SCRATCH_REGISTER_1
0180     li  SCRATCH_REGISTER_1, PPC_EXC_VR_OFFSET(23)
0181     stvx    v23, r1, SCRATCH_REGISTER_1
0182     li  SCRATCH_REGISTER_1, PPC_EXC_VR_OFFSET(24)
0183     stvx    v24, r1, SCRATCH_REGISTER_1
0184     li  SCRATCH_REGISTER_1, PPC_EXC_VR_OFFSET(25)
0185     stvx    v25, r1, SCRATCH_REGISTER_1
0186     li  SCRATCH_REGISTER_1, PPC_EXC_VR_OFFSET(26)
0187     stvx    v26, r1, SCRATCH_REGISTER_1
0188     li  SCRATCH_REGISTER_1, PPC_EXC_VR_OFFSET(27)
0189     stvx    v27, r1, SCRATCH_REGISTER_1
0190     li  SCRATCH_REGISTER_1, PPC_EXC_VR_OFFSET(28)
0191     stvx    v28, r1, SCRATCH_REGISTER_1
0192     li  SCRATCH_REGISTER_1, PPC_EXC_VR_OFFSET(29)
0193     stvx    v29, r1, SCRATCH_REGISTER_1
0194     li  SCRATCH_REGISTER_1, PPC_EXC_VR_OFFSET(30)
0195     stvx    v30, r1, SCRATCH_REGISTER_1
0196     li  SCRATCH_REGISTER_1, PPC_EXC_VR_OFFSET(31)
0197     stvx    v31, r1, SCRATCH_REGISTER_1
0198     mfvrsave    SCRATCH_REGISTER_1
0199     stw SCRATCH_REGISTER_1, PPC_EXC_VRSAVE_OFFSET(r1)
0200 #endif
0201
0202 #ifdef PPC_MULTILIB_FPU
0203     stfd    f0, PPC_EXC_FR_OFFSET(0)(r1)
0204     mffs    f0
0205     stfd    f0, PPC_EXC_FPSCR_OFFSET(r1)
0206     stfd    f1, PPC_EXC_FR_OFFSET(1)(r1)
0207     stfd    f2, PPC_EXC_FR_OFFSET(2)(r1)
0208     stfd    f3, PPC_EXC_FR_OFFSET(3)(r1)
0209     stfd    f4, PPC_EXC_FR_OFFSET(4)(r1)
0210     stfd    f5, PPC_EXC_FR_OFFSET(5)(r1)
0211     stfd    f6, PPC_EXC_FR_OFFSET(6)(r1)
0212     stfd    f7, PPC_EXC_FR_OFFSET(7)(r1)
0213     stfd    f8, PPC_EXC_FR_OFFSET(8)(r1)
0214     stfd    f9, PPC_EXC_FR_OFFSET(9)(r1)
0215     stfd    f10, PPC_EXC_FR_OFFSET(10)(r1)
0216     stfd    f11, PPC_EXC_FR_OFFSET(11)(r1)
0217     stfd    f12, PPC_EXC_FR_OFFSET(12)(r1)
0218     stfd    f13, PPC_EXC_FR_OFFSET(13)(r1)
0219     stfd    f14, PPC_EXC_FR_OFFSET(14)(r1)
0220     stfd    f15, PPC_EXC_FR_OFFSET(15)(r1)
0221     stfd    f16, PPC_EXC_FR_OFFSET(16)(r1)
0222     stfd    f17, PPC_EXC_FR_OFFSET(17)(r1)
0223     stfd    f18, PPC_EXC_FR_OFFSET(18)(r1)
0224     stfd    f19, PPC_EXC_FR_OFFSET(19)(r1)
0225     stfd    f20, PPC_EXC_FR_OFFSET(20)(r1)
0226     stfd    f21, PPC_EXC_FR_OFFSET(21)(r1)
0227     stfd    f22, PPC_EXC_FR_OFFSET(22)(r1)
0228     stfd    f23, PPC_EXC_FR_OFFSET(23)(r1)
0229     stfd    f24, PPC_EXC_FR_OFFSET(24)(r1)
0230     stfd    f25, PPC_EXC_FR_OFFSET(25)(r1)
0231     stfd    f26, PPC_EXC_FR_OFFSET(26)(r1)
0232     stfd    f27, PPC_EXC_FR_OFFSET(27)(r1)
0233     stfd    f28, PPC_EXC_FR_OFFSET(28)(r1)
0234     stfd    f29, PPC_EXC_FR_OFFSET(29)(r1)
0235     stfd    f30, PPC_EXC_FR_OFFSET(30)(r1)
0236     stfd    f31, PPC_EXC_FR_OFFSET(31)(r1)
0237 #endif
0238
0239     li  r3, 9
0240     addi    r4, r1, FRAME_LINK_SPACE
0241     b   _Terminate
0242     PPC64_NOP_FOR_LINKER_TOC_POINTER_RESTORE