shared/exceptions/ppc_exc_address.c

0001 /**
0002  * @file
0003  *
0004  * @ingroup ppc_exc
0005  *
0006  * @brief PowerPC Exceptions implementation.
0007  */
0008
0009 /*
0010  * Copyright (C) 1999 Eric Valette (valette@crf.canon.fr)
0011  *                    Canon Centre Recherche France.
0012  *
0013  * Copyright (C) 2009 embedded brains GmbH & Co. KG
0014  *
0015  * Enhanced by Jay Kulpinski <jskulpin@eng01.gdds.com>
0016  * to support 603, 603e, 604, 604e exceptions
0017  *
0018  * Moved to "libcpu/powerpc/new-exceptions" and consolidated
0019  * by Thomas Doerfler <Thomas.Doerfler@embedded-brains.de>
0020  * to be common for all PPCs with new exceptions.
0021  *
0022  * Derived from file "libcpu/powerpc/new-exceptions/raw_exception.c".
0023  *
0024  * The license and distribution terms for this file may be
0025  * found in the file LICENSE in this distribution or at
0026  * http://www.rtems.org/license/LICENSE.
0027  */
0028
0029 #include <rtems.h>
0030
0031 #include <bsp/vectors.h>
0032
0033 /*
0034  * XXX: These values are chosen to directly generate the vector offsets for an
0035  * e200z1 which has hard wired IVORs (IVOR0=0x00, IVOR1=0x10, IVOR2=0x20, ...).
0036  */
0037 static const uint8_t ivor_values [] = {
0038   [ASM_BOOKE_CRIT_VECTOR] = 0,
0039   [ASM_MACH_VECTOR] = 1,
0040   [ASM_PROT_VECTOR] = 2,
0041   [ASM_ISI_VECTOR] = 3,
0042   [ASM_EXT_VECTOR] = 4,
0043   [ASM_ALIGN_VECTOR] = 5,
0044   [ASM_PROG_VECTOR] = 6,
0045   [ASM_FLOAT_VECTOR] = 7,
0046   [ASM_SYS_VECTOR] = 8,
0047   [ASM_BOOKE_APU_VECTOR] = 9,
0048   [ASM_BOOKE_DEC_VECTOR] = 10,
0049   [ASM_BOOKE_FIT_VECTOR] = 11,
0050   [ASM_BOOKE_WDOG_VECTOR] = 12,
0051   [ASM_BOOKE_DTLBMISS_VECTOR] = 13,
0052   [ASM_BOOKE_ITLBMISS_VECTOR] = 14,
0053   [ASM_BOOKE_DEBUG_VECTOR] = 15,
0054   [ASM_E500_SPE_UNAVAILABLE_VECTOR] = 16,
0055   [ASM_E500_EMB_FP_DATA_VECTOR] = 17,
0056   [ASM_E500_EMB_FP_ROUND_VECTOR] = 18,
0057   [ASM_E500_PERFMON_VECTOR] = 19
0058 };
0059
0060 void *ppc_exc_vector_address(unsigned vector, void *vector_base)
0061 {
0062   uintptr_t vector_offset = vector << 8;
0063
0064   if (ppc_cpu_has_altivec()) {
0065     if (vector == ASM_60X_VEC_VECTOR) {
0066       vector_offset = ASM_60X_VEC_VECTOR_OFFSET;
0067     }
0068   }
0069
0070   if (ppc_cpu_is(PPC_405)) {
0071     switch (vector) {
0072       case ASM_BOOKE_FIT_VECTOR:
0073         vector_offset = ASM_PPC405_FIT_VECTOR_OFFSET;
0074         break;
0075       case ASM_BOOKE_WDOG_VECTOR:
0076         vector_offset = ASM_PPC405_WDOG_VECTOR_OFFSET;
0077         break;
0078       case ASM_TRACE_VECTOR:
0079         vector_offset = ASM_PPC405_TRACE_VECTOR_OFFSET;
0080         break;
0081       case ASM_PPC405_APU_UNAVAIL_VECTOR:
0082         vector_offset = ASM_60X_VEC_VECTOR_OFFSET;
0083       default:
0084         break;
0085     }
0086   }
0087
0088   if (
0089     ppc_cpu_is_bookE() == PPC_BOOKE_STD
0090       || ppc_cpu_is_bookE() == PPC_BOOKE_E500
0091   ) {
0092     if (vector < sizeof(ivor_values) / sizeof(ivor_values [0])) {
0093       vector_offset = ((uintptr_t) ivor_values [vector]) << 4;
0094     } else {
0095       vector_offset = 0;
0096     }
0097   }
0098
0099   return (void *) ((uintptr_t) vector_base + vector_offset);
0100 }