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0001 /* SPDX-License-Identifier: BSD-2-Clause */
0002 
0003 /**
0004  * @file
0005  *
0006  * @ingroup qoriq
0007  *
0008  * @brief BSP start.
0009  */
0010 
0011 /*
0012  * Copyright (C) 2010, 2017 embedded brains GmbH & Co. KG
0013  *
0014  * Redistribution and use in source and binary forms, with or without
0015  * modification, are permitted provided that the following conditions
0016  * are met:
0017  * 1. Redistributions of source code must retain the above copyright
0018  *    notice, this list of conditions and the following disclaimer.
0019  * 2. Redistributions in binary form must reproduce the above copyright
0020  *    notice, this list of conditions and the following disclaimer in the
0021  *    documentation and/or other materials provided with the distribution.
0022  *
0023  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
0024  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
0025  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
0026  * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
0027  * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
0028  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
0029  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
0030  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
0031  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
0032  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
0033  * POSSIBILITY OF SUCH DAMAGE.
0034  */
0035 
0036 #include <rtems/score/percpu.h>
0037 
0038 #include <bsp.h>
0039 
0040 #include <libcpu/powerpc-utility.h>
0041 
0042 #include <bsp/vectors.h>
0043 
0044 #if (QORIQ_INITIAL_MSR & MSR_FP) != 0
0045 #define INITIALIZE_FPU
0046 #endif
0047 
0048 #define FIRST_TLB 0
0049 #define SCRATCH_TLB QORIQ_TLB1_ENTRY_COUNT - 1
0050 #define INITIAL_MSR r14
0051 #define START_STACK r15
0052 #define SAVED_LINK_REGISTER r16
0053 #define FDT_REGISTER r17
0054 #define CPU_SELF r18
0055 
0056     .globl _start
0057 #ifdef RTEMS_SMP
0058 #if QORIQ_THREAD_COUNT > 1
0059     .globl _start_thread
0060 #endif
0061     .globl _start_secondary_processor
0062 #endif
0063     .globl bsp_exc_vector_base
0064 
0065     .section ".bsp_start_text", "ax"
0066 
0067 _start:
0068     mr  FDT_REGISTER, r3
0069     bl  .Linitearly
0070 
0071     /* Get start stack */
0072     LA  START_STACK, _ISR_Stack_area_begin
0073     LA  r3, _ISR_Stack_size
0074     add START_STACK, START_STACK, r3
0075 
0076     bl  .Linitmore
0077 
0078     /* Copy fast text */
0079     LA  r3, bsp_section_fast_text_begin
0080     LA  r4, bsp_section_fast_text_load_begin
0081     LA  r5, bsp_section_fast_text_size
0082     bl  .Lcopy
0083     LA  r3, bsp_section_fast_text_begin
0084     LA  r4, bsp_section_fast_text_size
0085     bl  rtems_cache_flush_multiple_data_lines
0086     PPC64_NOP_FOR_LINKER_TOC_POINTER_RESTORE
0087 
0088     /* Copy read-only data */
0089     LA  r3, bsp_section_rodata_begin
0090     LA  r4, bsp_section_rodata_load_begin
0091     LA  r5, bsp_section_rodata_size
0092     bl  .Lcopy
0093 
0094     /* Copy FDT into read-only data */
0095     mr  r3, FDT_REGISTER
0096     bl  bsp_fdt_copy
0097     PPC64_NOP_FOR_LINKER_TOC_POINTER_RESTORE
0098 
0099     /* Flush read-only data */
0100     LA  r3, bsp_section_rodata_begin
0101     LA  r4, bsp_section_rodata_size
0102     bl  rtems_cache_flush_multiple_data_lines
0103     PPC64_NOP_FOR_LINKER_TOC_POINTER_RESTORE
0104 
0105     /* Copy fast data */
0106     LA  r3, bsp_section_fast_data_begin
0107     LA  r4, bsp_section_fast_data_load_begin
0108     LA  r5, bsp_section_fast_data_size
0109     bl  .Lcopy
0110 
0111     /* Copy data */
0112     LA  r3, bsp_section_data_begin
0113     LA  r4, bsp_section_data_load_begin
0114     LA  r5, bsp_section_data_size
0115     bl  .Lcopy
0116 
0117     /* NULL pointer access protection (only core 0 has to do this) */
0118     mfspr   r3, BOOKE_PIR
0119     cmpwi   r3, 0
0120     bne .Lnull_area_setup_done
0121     LA  r3, bsp_section_start_begin
0122     SHIFT_RIGHT_IMMEDIATE   r3, r3, 2
0123     mtctr   r3
0124     li  r3, -4
0125     LWI r4, 0x44000002
0126 .Lnull_area_setup_loop:
0127     stwu    r4, 4(r3)
0128     bdnz    .Lnull_area_setup_loop
0129 .Lnull_area_setup_done:
0130 
0131     li  r3, 1
0132     bl  .Linitmmu
0133 
0134     /* Clear SBSS */
0135     LA  r3, bsp_section_sbss_begin
0136     LA  r4, bsp_section_sbss_size
0137     bl  bsp_start_zero
0138     PPC64_NOP_FOR_LINKER_TOC_POINTER_RESTORE
0139 
0140     /* Clear BSS */
0141     LA  r3, bsp_section_bss_begin
0142     LA  r4, bsp_section_bss_size
0143     bl  bsp_start_zero
0144     PPC64_NOP_FOR_LINKER_TOC_POINTER_RESTORE
0145 
0146 #ifndef __powerpc64__
0147     /* Set up EABI and SYSV environment */
0148     bl  __eabi
0149 #endif
0150 
0151     /* Clear command line */
0152     li  r3, 0
0153 
0154     bl  boot_card
0155     PPC64_NOP_FOR_LINKER_TOC_POINTER_RESTORE
0156 
0157 .Lcopy:
0158     PPC_REG_CMP r3, r4
0159     beqlr
0160     b   memcpy
0161     PPC64_NOP_FOR_LINKER_TOC_POINTER_RESTORE
0162 
0163 .Linitearly:
0164 #ifdef __powerpc64__
0165     /* Enable 64-bit computation mode for exceptions */
0166     mfspr   r0, BOOKE_EPCR
0167     oris    r0, r0, BOOKE_EPCR_ICM >> 16
0168     mtspr   BOOKE_EPCR, r0
0169 
0170     /* Enable 64-bit computation mode */
0171     mfmsr   r0
0172     oris    r0, r0, MSR_CM >> 16
0173     mtmsr   r0
0174     isync
0175 #endif
0176 
0177     /* Disable decrementer */
0178     mfspr   r0, BOOKE_TCR
0179     LWI r4, BOOKE_TCR_DIE
0180     andc    r0, r0, r4
0181     mtspr   BOOKE_TCR, r0
0182 
0183 #ifdef QORIQ_INITIAL_SPEFSCR
0184     /* SPEFSCR initialization */
0185     LWI r0, QORIQ_INITIAL_SPEFSCR
0186     mtspr   FSL_EIS_SPEFSCR, r0
0187 #endif
0188 
0189 #ifdef QORIQ_INITIAL_BUCSR
0190     /* BUCSR initialization */
0191     LWI r0, QORIQ_INITIAL_BUCSR
0192     mtspr   FSL_EIS_BUCSR, r0
0193     isync
0194 #endif
0195 
0196 #if defined(QORIQ_INITIAL_HID0) && !defined(QORIQ_IS_HYPERVISOR_GUEST)
0197     /* HID0 initialization */
0198     LWI r0, QORIQ_INITIAL_HID0
0199     mtspr   HID0, r0
0200 #endif
0201 
0202 #ifdef __powerpc64__
0203     LA32    r2, .TOC.
0204 #else
0205     /* Invalidate TLS anchor */
0206     li  r2, 0
0207 
0208     /* Set small-data anchor */
0209     LA  r13, _SDA_BASE_
0210 #endif
0211 
0212     SET_SELF_CPU_CONTROL    CPU_SELF, r5
0213 
0214     blr
0215 
0216 .Linitmore:
0217     mflr    SAVED_LINK_REGISTER
0218 
0219     /* Invalidate all TS1 MMU entries */
0220     li  r3, 1
0221     bl  qoriq_tlb1_invalidate_all_by_ts
0222     PPC64_NOP_FOR_LINKER_TOC_POINTER_RESTORE
0223 
0224     /* Add TS1 entry for the first 4GiB of RAM */
0225     li  r3, SCRATCH_TLB
0226     li  r4, FSL_EIS_MAS1_TS
0227     li  r5, FSL_EIS_MAS2_M
0228     li  r6, FSL_EIS_MAS3_SR | FSL_EIS_MAS3_SW | FSL_EIS_MAS3_SX
0229     li  r7, 0
0230     li  r8, 0
0231     li  r9, 11
0232     bl  qoriq_tlb1_write
0233     PPC64_NOP_FOR_LINKER_TOC_POINTER_RESTORE
0234 
0235     /* MSR initialization and use TS1 for address translation */
0236     LWI INITIAL_MSR, QORIQ_INITIAL_MSR
0237     ori r0, INITIAL_MSR, MSR_IS | MSR_DS
0238 #ifdef QORIQ_IS_HYPERVISOR_GUEST
0239     oris    r0, r0, MSR_GS >> 16
0240 #endif
0241     mtmsr   r0
0242     isync
0243 
0244     /*
0245      * Initialize start stack.  The stacks are statically allocated and
0246      * properly aligned.
0247      */
0248     subi    r1, START_STACK, PPC_DEFAULT_CACHE_LINE_SIZE
0249     li  r0, 0
0250     PPC_REG_STORE   r0, 0(r1)
0251 
0252 #ifdef INITIALIZE_FPU
0253     bl  .Linitfpu
0254 #endif
0255 
0256     mtlr    SAVED_LINK_REGISTER
0257     blr
0258 
0259 .Linitmmu:
0260     mflr    SAVED_LINK_REGISTER
0261 
0262     /* Configure MMU */
0263     li  r4, FIRST_TLB
0264     li  r5, SCRATCH_TLB
0265     bl  qoriq_mmu_config
0266     PPC64_NOP_FOR_LINKER_TOC_POINTER_RESTORE
0267     mtmsr   INITIAL_MSR
0268     isync
0269     li  r3, SCRATCH_TLB
0270     bl  qoriq_tlb1_invalidate
0271     PPC64_NOP_FOR_LINKER_TOC_POINTER_RESTORE
0272 
0273     mtlr    SAVED_LINK_REGISTER
0274     blr
0275 
0276 #ifdef INITIALIZE_FPU
0277     /*
0278      * Write a value to the FPRs to initialize the hidden tag bits.  See
0279      * also "Core Software Initialization Requirements" of the e500mc
0280      * reference manual for example.
0281      */
0282 .Linitfpu:
0283     li  r0, 0
0284     stw r0, 0(r1)
0285     stw r0, 4(r1)
0286     lfd f0, 0(r1)
0287     fmr f1, f0
0288     fmr f2, f0
0289     fmr f3, f0
0290     fmr f4, f0
0291     fmr f5, f0
0292     fmr f6, f0
0293     fmr f7, f0
0294     fmr f8, f0
0295     fmr f9, f0
0296     fmr f10, f0
0297     fmr f11, f0
0298     fmr f12, f0
0299     fmr f13, f0
0300     fmr f14, f0
0301     fmr f15, f0
0302     fmr f16, f0
0303     fmr f17, f0
0304     fmr f18, f0
0305     fmr f19, f0
0306     fmr f20, f0
0307     fmr f21, f0
0308     fmr f22, f0
0309     fmr f23, f0
0310     fmr f24, f0
0311     fmr f25, f0
0312     fmr f26, f0
0313     fmr f27, f0
0314     fmr f28, f0
0315     fmr f29, f0
0316     fmr f30, f0
0317     fmr f31, f0
0318     blr
0319 #endif
0320 
0321 #ifdef RTEMS_SMP
0322 #if QORIQ_THREAD_COUNT > 1
0323 _start_thread:
0324     /* Adjust PIR */
0325     mfspr   r0, BOOKE_PIR
0326     srawi   r0, r0, 2
0327     ori r0, r0, 1
0328     mtspr   BOOKE_PIR, r0
0329 
0330     bl  .Linitearly
0331 
0332     /* Initialize start stack */
0333     PPC_REG_LOAD    r3, PER_CPU_INTERRUPT_STACK_HIGH(CPU_SELF)
0334     subi    r1, r3, PPC_MINIMUM_STACK_FRAME_SIZE
0335     CLEAR_RIGHT_IMMEDIATE   r1, r1, PPC_STACK_ALIGN_POWER
0336     li  r0, 0
0337     PPC_REG_STORE   r0, 0(r1)
0338 
0339 #ifdef INITIALIZE_FPU
0340     bl  .Linitfpu
0341 #endif
0342 
0343     mr  r3, CPU_SELF
0344     b   qoriq_start_thread
0345     PPC64_NOP_FOR_LINKER_TOC_POINTER_RESTORE
0346 #endif
0347 _start_secondary_processor:
0348     bl  .Linitearly
0349 
0350     /* Get start stack */
0351     mr  START_STACK, r3
0352 
0353     bl  .Linitmore
0354     li  r3, 0
0355     bl  .Linitmmu
0356     mr  r3, CPU_SELF
0357     b   bsp_start_on_secondary_processor
0358     PPC64_NOP_FOR_LINKER_TOC_POINTER_RESTORE
0359 #endif /* RTEMS_SMP */
0360 
0361 #ifdef __powerpc64__
0362 #define START_NOP_FOR_LINKER_TOC_POINTER_RESTORE nop; nop; nop; nop
0363 #else
0364 #define START_NOP_FOR_LINKER_TOC_POINTER_RESTORE
0365 #endif
0366 
0367     /* Exception vector prologues area */
0368     .section ".bsp_start_text", "ax"
0369     .align 4
0370 bsp_exc_vector_base:
0371     /* Critical input */
0372     PPC_REG_STORE_UPDATE    r1, -EXC_GENERIC_SIZE(r1)
0373     PPC_REG_STORE   r3, GPR3_OFFSET(r1)
0374     li  r3, 0
0375     b   ppc_exc_fatal_critical
0376     START_NOP_FOR_LINKER_TOC_POINTER_RESTORE
0377     /* Machine check */
0378     PPC_REG_STORE_UPDATE    r1, -EXC_GENERIC_SIZE(r1)
0379     PPC_REG_STORE   r3, GPR3_OFFSET(r1)
0380     li  r3, 1
0381     b   ppc_exc_fatal_machine_check
0382     START_NOP_FOR_LINKER_TOC_POINTER_RESTORE
0383     /* Data storage */
0384     PPC_REG_STORE_UPDATE    r1, -EXC_GENERIC_SIZE(r1)
0385     PPC_REG_STORE   r3, GPR3_OFFSET(r1)
0386     li  r3, 2
0387     b   ppc_exc_fatal_normal
0388     START_NOP_FOR_LINKER_TOC_POINTER_RESTORE
0389     /* Instruction storage */
0390     PPC_REG_STORE_UPDATE    r1, -EXC_GENERIC_SIZE(r1)
0391     PPC_REG_STORE   r3, GPR3_OFFSET(r1)
0392     li  r3, 3
0393     b   ppc_exc_fatal_normal
0394     START_NOP_FOR_LINKER_TOC_POINTER_RESTORE
0395     /* External input */
0396     PPC_REG_STORE_UPDATE    r1, -PPC_EXC_INTERRUPT_FRAME_SIZE(r1)
0397     PPC_REG_STORE   r3, PPC_EXC_GPR3_PROLOGUE_OFFSET(r1)
0398     li  r3, 4
0399     b   ppc_exc_interrupt
0400     START_NOP_FOR_LINKER_TOC_POINTER_RESTORE
0401     /* Alignment */
0402     PPC_REG_STORE_UPDATE    r1, -EXC_GENERIC_SIZE(r1)
0403     PPC_REG_STORE   r3, GPR3_OFFSET(r1)
0404     li  r3, 5
0405     b   ppc_exc_fatal_normal
0406     START_NOP_FOR_LINKER_TOC_POINTER_RESTORE
0407     /* Program */
0408     PPC_REG_STORE_UPDATE    r1, -EXC_GENERIC_SIZE(r1)
0409     PPC_REG_STORE   r3, GPR3_OFFSET(r1)
0410     li  r3, 6
0411     b   ppc_exc_fatal_normal
0412     START_NOP_FOR_LINKER_TOC_POINTER_RESTORE
0413 #ifdef __PPC_CPU_E6500__
0414     /* Floating-point unavailable */
0415     PPC_REG_STORE_UPDATE    r1, -EXC_GENERIC_SIZE(r1)
0416     PPC_REG_STORE   r3, GPR3_OFFSET(r1)
0417     li  r3, 7
0418     b   ppc_exc_fatal_normal
0419     START_NOP_FOR_LINKER_TOC_POINTER_RESTORE
0420 #endif
0421     /* System call */
0422     PPC_REG_STORE_UPDATE    r1, -EXC_GENERIC_SIZE(r1)
0423     PPC_REG_STORE   r3, GPR3_OFFSET(r1)
0424     li  r3, 8
0425     b   ppc_exc_fatal_normal
0426     START_NOP_FOR_LINKER_TOC_POINTER_RESTORE
0427 #ifdef __PPC_CPU_E6500__
0428     /* APU unavailable */
0429     PPC_REG_STORE_UPDATE    r1, -EXC_GENERIC_SIZE(r1)
0430     PPC_REG_STORE   r3, GPR3_OFFSET(r1)
0431     li  r3, 9
0432     b   ppc_exc_fatal_normal
0433     START_NOP_FOR_LINKER_TOC_POINTER_RESTORE
0434 #endif
0435     /* Decrementer */
0436 #ifdef QORIQ_IS_HYPERVISOR_GUEST
0437     PPC_REG_STORE_UPDATE    r1, -PPC_EXC_INTERRUPT_FRAME_SIZE(r1)
0438     PPC_REG_STORE   r3, PPC_EXC_GPR3_PROLOGUE_OFFSET(r1)
0439     li  r3, 10
0440     b   ppc_exc_interrupt
0441 #else
0442     PPC_REG_STORE_UPDATE    r1, -EXC_GENERIC_SIZE(r1)
0443     PPC_REG_STORE   r3, GPR3_OFFSET(r1)
0444     li  r3, 10
0445     b   ppc_exc_fatal_normal
0446 #endif
0447     START_NOP_FOR_LINKER_TOC_POINTER_RESTORE
0448     /* Fixed-interval timer interrupt */
0449     PPC_REG_STORE_UPDATE    r1, -EXC_GENERIC_SIZE(r1)
0450     PPC_REG_STORE   r3, GPR3_OFFSET(r1)
0451     li  r3, 11
0452     b   ppc_exc_fatal_normal
0453     START_NOP_FOR_LINKER_TOC_POINTER_RESTORE
0454     /* Watchdog timer interrupt */
0455     PPC_REG_STORE_UPDATE    r1, -EXC_GENERIC_SIZE(r1)
0456     PPC_REG_STORE   r3, GPR3_OFFSET(r1)
0457     li  r3, 12
0458     b   ppc_exc_fatal_critical
0459     START_NOP_FOR_LINKER_TOC_POINTER_RESTORE
0460     /* Data TLB error */
0461     PPC_REG_STORE_UPDATE    r1, -EXC_GENERIC_SIZE(r1)
0462     PPC_REG_STORE   r3, GPR3_OFFSET(r1)
0463     li  r3, 13
0464     b   ppc_exc_fatal_normal
0465     START_NOP_FOR_LINKER_TOC_POINTER_RESTORE
0466     /* Instruction TLB error */
0467     PPC_REG_STORE_UPDATE    r1, -EXC_GENERIC_SIZE(r1)
0468     PPC_REG_STORE   r3, GPR3_OFFSET(r1)
0469     li  r3, 14
0470     b   ppc_exc_fatal_normal
0471     START_NOP_FOR_LINKER_TOC_POINTER_RESTORE
0472     /* Debug */
0473     PPC_REG_STORE_UPDATE    r1, -EXC_GENERIC_SIZE(r1)
0474     PPC_REG_STORE   r3, GPR3_OFFSET(r1)
0475     li  r3, 15
0476     b   ppc_exc_fatal_debug
0477     START_NOP_FOR_LINKER_TOC_POINTER_RESTORE
0478     /* SPE APU unavailable or AltiVec unavailable */
0479     PPC_REG_STORE_UPDATE    r1, -EXC_GENERIC_SIZE(r1)
0480     PPC_REG_STORE   r3, GPR3_OFFSET(r1)
0481     li  r3, 32
0482     b   ppc_exc_fatal_normal
0483     START_NOP_FOR_LINKER_TOC_POINTER_RESTORE
0484     /* SPE floating-point data exception or AltiVec assist */
0485     PPC_REG_STORE_UPDATE    r1, -EXC_GENERIC_SIZE(r1)
0486     PPC_REG_STORE   r3, GPR3_OFFSET(r1)
0487     li  r3, 33
0488     b   ppc_exc_fatal_normal
0489     START_NOP_FOR_LINKER_TOC_POINTER_RESTORE
0490 #ifndef __PPC_CPU_E6500__
0491     /* SPE floating-point round exception */
0492     PPC_REG_STORE_UPDATE    r1, -EXC_GENERIC_SIZE(r1)
0493     PPC_REG_STORE   r3, GPR3_OFFSET(r1)
0494     li  r3, 34
0495     b   ppc_exc_fatal_normal
0496     START_NOP_FOR_LINKER_TOC_POINTER_RESTORE
0497 #endif
0498     /* Performance monitor */
0499     PPC_REG_STORE_UPDATE    r1, -EXC_GENERIC_SIZE(r1)
0500     PPC_REG_STORE   r3, GPR3_OFFSET(r1)
0501     li  r3, 35
0502     b   ppc_exc_fatal_normal
0503     START_NOP_FOR_LINKER_TOC_POINTER_RESTORE
0504 #ifdef __PPC_CPU_E6500__
0505     /* Processor doorbell interrupt */
0506 #if defined(QORIQ_IS_HYPERVISOR_GUEST) && defined(RTEMS_SMP)
0507     PPC_REG_STORE_UPDATE    r1, -PPC_EXC_INTERRUPT_FRAME_SIZE(r1)
0508     PPC_REG_STORE   r3, PPC_EXC_GPR3_PROLOGUE_OFFSET(r1)
0509     li  r3, 36
0510     b   ppc_exc_interrupt
0511 #else
0512     PPC_REG_STORE_UPDATE    r1, -EXC_GENERIC_SIZE(r1)
0513     PPC_REG_STORE   r3, GPR3_OFFSET(r1)
0514     li  r3, 36
0515     b   ppc_exc_fatal_normal
0516 #endif
0517     START_NOP_FOR_LINKER_TOC_POINTER_RESTORE
0518     /* Processor doorbell critical interrupt */
0519     PPC_REG_STORE_UPDATE    r1, -EXC_GENERIC_SIZE(r1)
0520     PPC_REG_STORE   r3, GPR3_OFFSET(r1)
0521     li  r3, 37
0522     b   ppc_exc_fatal_critical
0523     START_NOP_FOR_LINKER_TOC_POINTER_RESTORE
0524     /* Guest processor doorbell */
0525     PPC_REG_STORE_UPDATE    r1, -EXC_GENERIC_SIZE(r1)
0526     PPC_REG_STORE   r3, GPR3_OFFSET(r1)
0527     li  r3, 38
0528     b   ppc_exc_fatal_normal
0529     START_NOP_FOR_LINKER_TOC_POINTER_RESTORE
0530     /* Guest processor doorbell critical and machine check */
0531     PPC_REG_STORE_UPDATE    r1, -EXC_GENERIC_SIZE(r1)
0532     PPC_REG_STORE   r3, GPR3_OFFSET(r1)
0533     li  r3, 39
0534     b   ppc_exc_fatal_critical
0535     START_NOP_FOR_LINKER_TOC_POINTER_RESTORE
0536     /* Hypervisor system call */
0537     PPC_REG_STORE_UPDATE    r1, -EXC_GENERIC_SIZE(r1)
0538     PPC_REG_STORE   r3, GPR3_OFFSET(r1)
0539     li  r3, 40
0540     b   ppc_exc_fatal_normal
0541     START_NOP_FOR_LINKER_TOC_POINTER_RESTORE
0542     /* Hypervisor privilege */
0543     PPC_REG_STORE_UPDATE    r1, -EXC_GENERIC_SIZE(r1)
0544     PPC_REG_STORE   r3, GPR3_OFFSET(r1)
0545     li  r3, 41
0546     b   ppc_exc_fatal_normal
0547     START_NOP_FOR_LINKER_TOC_POINTER_RESTORE
0548     /* LRAT error */
0549     PPC_REG_STORE_UPDATE    r1, -EXC_GENERIC_SIZE(r1)
0550     PPC_REG_STORE   r3, GPR3_OFFSET(r1)
0551     li  r3, 42
0552     b   ppc_exc_fatal_normal
0553     START_NOP_FOR_LINKER_TOC_POINTER_RESTORE
0554 #endif
0555 
0556 /* Symbol provided for debugging and tracing */
0557 bsp_exc_vector_end:
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