qoriq/start/restart.S

0001 /* SPDX-License-Identifier: BSD-2-Clause */
0002
0003 /*
0004  * Copyright (c) 2016 embedded brains GmbH & Co. KG
0005  *
0006  * Redistribution and use in source and binary forms, with or without
0007  * modification, are permitted provided that the following conditions
0008  * are met:
0009  * 1. Redistributions of source code must retain the above copyright
0010  *    notice, this list of conditions and the following disclaimer.
0011  * 2. Redistributions in binary form must reproduce the above copyright
0012  *    notice, this list of conditions and the following disclaimer in the
0013  *    documentation and/or other materials provided with the distribution.
0014  *
0015  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
0016  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
0017  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
0018  * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
0019  * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
0020  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
0021  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
0022  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
0023  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
0024  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
0025  * POSSIBILITY OF SUCH DAMAGE.
0026  */
0027
0028 #include <libcpu/powerpc-utility.h>
0029
0030 #define FIRST_TLB 0
0031
0032 #define SCRATCH_TLB QORIQ_TLB1_ENTRY_COUNT - 1
0033
0034     .global qoriq_restart_secondary_processor
0035
0036     .section ".bsp_start_text", "ax"
0037
0038 qoriq_restart_secondary_processor:
0039
0040     mr  r14, r3
0041
0042     /* Invalidate all TS1 MMU entries */
0043     li  r3, 1
0044     bl  qoriq_tlb1_invalidate_all_by_ts
0045
0046     /* Add TS1 entry for the first 4GiB of RAM */
0047     li  r3, SCRATCH_TLB
0048     li  r4, FSL_EIS_MAS1_TS
0049     li  r5, FSL_EIS_MAS2_I
0050     li  r6, FSL_EIS_MAS3_SR | FSL_EIS_MAS3_SW | FSL_EIS_MAS3_SX
0051     li  r7, 0
0052     li  r8, 0
0053     li  r9, 11
0054     bl  qoriq_tlb1_write
0055
0056     bl  qoriq_l1cache_invalidate
0057
0058     /* Set MSR and use TS1 for address translation */
0059     LWI r0, QORIQ_INITIAL_MSR | MSR_IS | MSR_DS
0060     mtmsr   r0
0061     isync
0062
0063     /* Invalidate all TS0 MMU entries */
0064     li  r3, 0
0065     bl  qoriq_tlb1_invalidate_all_by_ts
0066
0067     /* Add TS0 entry for the first 4GiB of RAM */
0068     li  r3, FIRST_TLB
0069     li  r4, 0
0070     li  r5, FSL_EIS_MAS2_I
0071     li  r6, FSL_EIS_MAS3_SR | FSL_EIS_MAS3_SW | FSL_EIS_MAS3_SX
0072     li  r7, 0
0073     li  r8, 0
0074     li  r9, 11
0075     bl  qoriq_tlb1_write
0076
0077     /* Use TS0 for address translation */
0078     LWI r0, QORIQ_INITIAL_MSR
0079     mtmsr   r0
0080     isync
0081
0082     bl  qoriq_l1cache_invalidate
0083
0084     /* Wait for restart request */
0085     li  r0, 0
0086 .Lrestartagain:
0087     lwz r4, 4(r14)
0088     cmpw    r0, r4
0089     beq .Lrestartagain
0090     isync
0091     mtctr   r4
0092     lwz r3, 12(r14)
0093     bctr