qoriq/start/l1cache.S

0001 /* SPDX-License-Identifier: BSD-2-Clause */
0002
0003 /*
0004  * Copyright (C) 2015, 2016 embedded brains GmbH & Co. KG
0005  *
0006  * Redistribution and use in source and binary forms, with or without
0007  * modification, are permitted provided that the following conditions
0008  * are met:
0009  * 1. Redistributions of source code must retain the above copyright
0010  *    notice, this list of conditions and the following disclaimer.
0011  * 2. Redistributions in binary form must reproduce the above copyright
0012  *    notice, this list of conditions and the following disclaimer in the
0013  *    documentation and/or other materials provided with the distribution.
0014  *
0015  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
0016  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
0017  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
0018  * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
0019  * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
0020  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
0021  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
0022  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
0023  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
0024  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
0025  * POSSIBILITY OF SUCH DAMAGE.
0026  */
0027
0028 #include <libcpu/powerpc-utility.h>
0029
0030     .global qoriq_l1cache_invalidate
0031
0032     .section ".bsp_start_text", "ax"
0033
0034 qoriq_l1cache_invalidate:
0035
0036     /* Invalidate L1 data cache */
0037     mfspr   r3, FSL_EIS_L1CSR0
0038     ori r3, r3, FSL_EIS_L1CSR0_CFI
0039     mtspr   FSL_EIS_L1CSR0, r3
0040 1:
0041     mfspr   r3, FSL_EIS_L1CSR0
0042     andi.   r3, r3, FSL_EIS_L1CSR0_CFI
0043     bne 1b
0044     isync
0045
0046     /* Invalidate L1 instruction cache */
0047     mfspr   r3, FSL_EIS_L1CSR1
0048     ori r3, r3, FSL_EIS_L1CSR1_ICFI
0049     mtspr   FSL_EIS_L1CSR1, r3
0050 1:
0051     mfspr   r3, FSL_EIS_L1CSR1
0052     andi.   r3, r3, FSL_EIS_L1CSR1_ICFI
0053     bne 1b
0054     isync
0055
0056     blr