Back to home page

LXR

 
 

    


File indexing completed on 2025-05-11 08:23:57

0001 /* SPDX-License-Identifier: BSD-2-Clause */
0002 
0003 /**
0004  * @file
0005  *
0006  * @ingroup RTEMSBSPsPowerPCQorIQ
0007  *
0008  * @brief Support file for Timer Test 27.
0009  */
0010 
0011 /*
0012  * Copyright (C) 2010, 2015 embedded brains GmbH & Co. KG
0013  *
0014  * Redistribution and use in source and binary forms, with or without
0015  * modification, are permitted provided that the following conditions
0016  * are met:
0017  * 1. Redistributions of source code must retain the above copyright
0018  *    notice, this list of conditions and the following disclaimer.
0019  * 2. Redistributions in binary form must reproduce the above copyright
0020  *    notice, this list of conditions and the following disclaimer in the
0021  *    documentation and/or other materials provided with the distribution.
0022  *
0023  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
0024  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
0025  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
0026  * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
0027  * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
0028  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
0029  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
0030  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
0031  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
0032  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
0033  * POSSIBILITY OF SUCH DAMAGE.
0034  */
0035 
0036 #ifndef _RTEMS_TMTEST27
0037   #error "This is an RTEMS internal file you must not include directly."
0038 #endif /* _RTEMS_TMTEST27 */
0039 
0040 #ifndef TMTESTS_TM27_H
0041 #define TMTESTS_TM27_H
0042 
0043 #include <libcpu/powerpc-utility.h>
0044 
0045 #include <bsp/irq.h>
0046 #include <bsp/qoriq.h>
0047 
0048 #define MUST_WAIT_FOR_INTERRUPT 1
0049 
0050 #define IPI_INDEX_LOW 1
0051 
0052 #define IPI_INDEX_HIGH 2
0053 
0054 static inline void Install_tm27_vector( rtems_interrupt_handler handler )
0055 {
0056   static rtems_interrupt_entry entry_low;
0057   static rtems_interrupt_entry entry_high;
0058   rtems_vector_number low = QORIQ_IRQ_IPI_0 + IPI_INDEX_LOW;
0059   rtems_vector_number high = QORIQ_IRQ_IPI_0 + IPI_INDEX_HIGH;
0060 
0061   (void) rtems_interrupt_set_priority(low, 14);
0062   (void) rtems_interrupt_set_priority(high, 13);
0063 
0064   rtems_interrupt_entry_initialize(
0065     &entry_low,
0066     handler,
0067     NULL,
0068     "tm17 low"
0069   );
0070   (void) rtems_interrupt_entry_install(
0071     low,
0072     RTEMS_INTERRUPT_UNIQUE,
0073     &entry_low
0074   );
0075 
0076   rtems_interrupt_entry_initialize(
0077     &entry_high,
0078     handler,
0079     NULL,
0080     "tm17 high"
0081   );
0082   (void) rtems_interrupt_entry_install(
0083     high,
0084     RTEMS_INTERRUPT_UNIQUE,
0085     &entry_high
0086   );
0087 }
0088 
0089 static inline void qoriq_tm27_cause(uint32_t ipi_index)
0090 {
0091   uint32_t self = ppc_processor_id();
0092 
0093   qoriq.pic.per_cpu[self].ipidr[ipi_index].reg = UINT32_C(1) << self;
0094 }
0095 
0096 static inline void Cause_tm27_intr(void)
0097 {
0098   qoriq_tm27_cause(IPI_INDEX_LOW);
0099 }
0100 
0101 static inline void Clear_tm27_intr(void)
0102 {
0103   /* Nothing to do */
0104 }
0105 
0106 static inline inline void Lower_tm27_intr(void)
0107 {
0108   qoriq_tm27_cause(IPI_INDEX_HIGH);
0109 }
0110 
0111 #endif /* TMTESTS_TM27_H */