qemuppc/start/bspstart.c

0001 /* SPDX-License-Identifier: BSD-2-Clause */
0002
0003 /*
0004  *  This set of routines starts the application.  It includes application,
0005  *  board, and monitor specific initialization and configuration.
0006  *  The generic CPU dependent initialization has been performed
0007  *  before any of these are invoked.
0008  *
0009  *  COPYRIGHT (c) 1989-2008.
0010  *  On-Line Applications Research Corporation (OAR).
0011  *
0012  * Redistribution and use in source and binary forms, with or without
0013  * modification, are permitted provided that the following conditions
0014  * are met:
0015  * 1. Redistributions of source code must retain the above copyright
0016  *    notice, this list of conditions and the following disclaimer.
0017  * 2. Redistributions in binary form must reproduce the above copyright
0018  *    notice, this list of conditions and the following disclaimer in the
0019  *    documentation and/or other materials provided with the distribution.
0020  *
0021  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
0022  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
0023  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
0024  * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
0025  * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
0026  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
0027  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
0028  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
0029  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
0030  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
0031  * POSSIBILITY OF SUCH DAMAGE.
0032  */
0033
0034 #include <string.h>
0035 #include <fcntl.h>
0036
0037 #include <rtems/counter.h>
0038
0039 #include <libcpu/bat.h>
0040 #include <libcpu/spr.h>
0041 #include <libcpu/powerpc-utility.h>
0042
0043 #include <bsp.h>
0044 #include <bsp/irq.h>
0045 #include <bsp/vectors.h>
0046 #include <bsp/bootcard.h>
0047 #include <bsp/irq-generic.h>
0048
0049 /*
0050  * CPU Bus Frequency
0051  */
0052 unsigned int BSP_bus_frequency;
0053
0054 /* Configuration parameter for clock driver */
0055 uint32_t bsp_time_base_frequency;
0056
0057 /* Legacy */
0058 uint32_t bsp_clicks_per_usec;
0059
0060 /*
0061  * Memory on this board.
0062  */
0063 extern char RamSize[];
0064 uint32_t BSP_mem_size = (uint32_t)RamSize;
0065
0066 /* Default decrementer exception handler */
0067 static int default_decrementer_exception_handler( BSP_Exception_frame *frame, unsigned number)
0068 {
0069   ppc_set_decrementer_register(UINT32_MAX);
0070
0071   return 0;
0072 }
0073
0074 uint32_t _CPU_Counter_frequency(void)
0075 {
0076   return bsp_time_base_frequency;
0077 }
0078
0079 /*
0080  *  bsp_start
0081  *
0082  *  This routine does the bulk of the system initialization.
0083  */
0084
0085 void bsp_start( void )
0086 {
0087   rtems_status_code sc = RTEMS_SUCCESSFUL;
0088
0089   /*
0090    * Note we can not get CPU identification dynamically, so
0091    * force current_ppc_cpu.
0092    */
0093   current_ppc_cpu = PPC_PSIM;
0094
0095   /*
0096    *  initialize the device driver parameters
0097    * assume we are running with 20MHz bus
0098    * this should speed up some tests :-)
0099    */
0100   BSP_bus_frequency        = 20;
0101   bsp_time_base_frequency  = 20000000;
0102   bsp_clicks_per_usec      = BSP_bus_frequency;
0103
0104   BSP_mem_size = (uint32_t )RamSize;
0105
0106   ppc_exc_initialize();
0107
0108   /* Install default handler for the decrementer exception */
0109   sc = ppc_exc_set_handler( ASM_DEC_VECTOR, default_decrementer_exception_handler);
0110   if (sc != RTEMS_SUCCESSFUL) {
0111     rtems_panic("cannot install decrementer exception handler");
0112   }
0113
0114   /* Initalize interrupt support */
0115   bsp_interrupt_initialize();
0116
0117 #if 0
0118   /*
0119    * Setup BATs and enable MMU
0120    */
0121   /* Memory */
0122   setdbat(0, 0x0<<24, 0x0<<24, 2<<24, _PAGE_RW);
0123   setibat(0, 0x0<<24, 0x0<<24, 2<<24,        0);
0124   /* PCI    */
0125   setdbat(1, 0x8<<24, 0x8<<24, 1<<24,  IO_PAGE);
0126   setdbat(2, 0xc<<24, 0xc<<24, 1<<24,  IO_PAGE);
0127
0128   _write_MSR(_read_MSR() | MSR_DR | MSR_IR);
0129   __asm__ volatile("sync; isync");
0130 #endif
0131 }