psim/start/bspstart.c

0001 /* SPDX-License-Identifier: BSD-2-Clause */
0002
0003 /*
0004  *  This set of routines starts the application.  It includes application,
0005  *  board, and monitor specific initialization and configuration.
0006  *  The generic CPU dependent initialization has been performed
0007  *  before any of these are invoked.
0008  *
0009  *  COPYRIGHT (c) 1989-2008.
0010  *  On-Line Applications Research Corporation (OAR).
0011  *
0012  * Redistribution and use in source and binary forms, with or without
0013  * modification, are permitted provided that the following conditions
0014  * are met:
0015  * 1. Redistributions of source code must retain the above copyright
0016  *    notice, this list of conditions and the following disclaimer.
0017  * 2. Redistributions in binary form must reproduce the above copyright
0018  *    notice, this list of conditions and the following disclaimer in the
0019  *    documentation and/or other materials provided with the distribution.
0020  *
0021  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
0022  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
0023  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
0024  * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
0025  * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
0026  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
0027  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
0028  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
0029  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
0030  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
0031  * POSSIBILITY OF SUCH DAMAGE.
0032  */
0033
0034 #include <string.h>
0035 #include <fcntl.h>
0036 #include <bsp.h>
0037 #include <bsp/irq.h>
0038 #include <psim.h>
0039 #include <bsp/bootcard.h>
0040 #include <bsp/linker-symbols.h>
0041 #include <rtems/bspIo.h>
0042 #include <rtems/counter.h>
0043 #include <rtems/powerpc/powerpc.h>
0044
0045 #include <libcpu/cpuIdent.h>
0046 #include <libcpu/bat.h>
0047 #include <libcpu/spr.h>
0048
0049 SPR_RW(SPRG1)
0050
0051 /*  On psim, each click of the decrementer register corresponds
0052  *  to 1 instruction.  By setting this to 100, we are indicating
0053  *  that we are assuming it can execute 100 instructions per
0054  *  microsecond.  This corresponds to sustaining 1 instruction
0055  *  per cycle at 100 Mhz.  Whether this is a good guess or not
0056  *  is anyone's guess.
0057  */
0058 extern int PSIM_INSTRUCTIONS_PER_MICROSECOND[];
0059
0060 /*
0061  * PCI Bus Frequency
0062  */
0063 unsigned int BSP_bus_frequency;
0064
0065 /*
0066  *  Driver configuration parameters
0067  */
0068 uint32_t   bsp_clicks_per_usec;
0069
0070 /*
0071  * Memory on this board.
0072  */
0073 uint32_t BSP_mem_size = (uint32_t)RamSize;
0074
0075 /*
0076  * Time base divisior (how many tick for 1 second).
0077  */
0078 unsigned int BSP_time_base_divisor;
0079
0080 extern unsigned long __rtems_end[];
0081
0082 uint32_t _CPU_Counter_frequency(void)
0083 {
0084   return bsp_clicks_per_usec * 1000000;
0085 }
0086
0087 /*
0088  *  bsp_start
0089  *
0090  *  This routine does the bulk of the system initialization.
0091  */
0092 void bsp_start( void )
0093 {
0094   /*
0095    * Note we can not get CPU identification dynamically.
0096    * PVR has to be set to PPC_PSIM (0xfffe) from the device
0097    * file.
0098    */
0099
0100   get_ppc_cpu_type();
0101
0102   /*
0103    *  initialize the device driver parameters
0104    */
0105   BSP_bus_frequency        = (unsigned int)PSIM_INSTRUCTIONS_PER_MICROSECOND;
0106   bsp_clicks_per_usec      = BSP_bus_frequency;
0107   BSP_time_base_divisor    = 1;
0108
0109   ppc_exc_initialize_with_vector_base(
0110     (uintptr_t) _ISR_Stack_area_begin,
0111     (void *) 0xfff00000
0112   );
0113
0114   /*
0115    * Initalize RTEMS IRQ system
0116    */
0117   BSP_rtems_irq_mng_init(0);
0118
0119   /*
0120    * Setup BATs and enable MMU
0121    */
0122   /* Memory */
0123   setdbat(0, 0x0<<28, 0x0<<28, 1<<28, _PAGE_RW);
0124   setibat(0, 0x0<<28, 0x0<<28, 1<<28,        0);
0125   /* PCI    */
0126   setdbat(1, 0x08<<24, 0x08<<24, 1<<24,  IO_PAGE);
0127   setdbat(2, 0xfc<<24, 0xfc<<24, 1<<24,  IO_PAGE);
0128
0129   _write_MSR(_read_MSR() | MSR_DR | MSR_IR);
0130   __asm__ volatile("sync; isync");
0131
0132 }